{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:20:54Z","timestamp":1758892854588,"version":"3.41.0"},"reference-count":46,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2013,3,10]],"date-time":"2013-03-10T00:00:00Z","timestamp":1362873600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2013,3,10]]},"abstract":"<jats:p>Recently, system designers are facing the challenge of developing systems that have diverse features, are more complex and more powerful, with less power consumption and reduced time to market. These contradictory constraints have forced technology providers to pursue design solutions that will allow design teams to meet the above design targets. In that respect, this paper introduces an innovative technology platform, called MORPHEUS, which intents to provide complete design framework for dealing with the aforementioned challenges. MORPHEUS consists of a state of the art architecture that encompasses heterogeneous reconfigurable accelerators for implementing on the same hardware architecture applications with varying characteristics and a tool chain that, through a software oriented approach, eases the implementation of highly complex applications with heterogeneous characteristics. The proposed approach has been tested and evaluated through state of the art cases studies borrowed from complementary application domains.<\/jats:p>","DOI":"10.1145\/2442116.2442120","type":"journal-article","created":{"date-parts":[[2013,4,9]],"date-time":"2013-04-09T12:17:58Z","timestamp":1365509878000},"page":"1-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":25,"title":["MORPHEUS"],"prefix":"10.1145","volume":"12","author":[{"given":"Nikolaos S.","family":"Voros","sequence":"first","affiliation":[{"name":"Technological Educational Institute of Mesolonghi"}]},{"given":"Michael","family":"H\u00fcbner","sequence":"additional","affiliation":[{"name":"University of Karlsruhe (TH)"}]},{"given":"J\u00fcrgen","family":"Becker","sequence":"additional","affiliation":[{"name":"University of Karlsruhe (TH)"}]},{"given":"Matthias","family":"K\u00fchnle","sequence":"additional","affiliation":[{"name":"University of Karlsruhe (TH)"}]},{"given":"Florian","family":"Thomaitiv","sequence":"additional","affiliation":[{"name":"University of Karlsruhe (TH)"}]},{"given":"Arnaud","family":"Grasset","sequence":"additional","affiliation":[{"name":"Thales Research &amp; Technology"}]},{"given":"Paul","family":"Brelet","sequence":"additional","affiliation":[{"name":"Thales Research &amp; Technology"}]},{"given":"Philippe","family":"Bonnot","sequence":"additional","affiliation":[{"name":"Thales Research &amp; Technology"}]},{"given":"Fabio","family":"Campi","sequence":"additional","affiliation":[{"name":"ST Microelectronics"}]},{"given":"Eberhard","family":"Sch\u00fcler","sequence":"additional","affiliation":[{"name":"PACT XPP Technologies"}]},{"given":"Henning","family":"Sahlbach","sequence":"additional","affiliation":[{"name":"Technical University of Braunschweig"}]},{"given":"Sean","family":"Whitty","sequence":"additional","affiliation":[{"name":"Technical University of Braunschweig"}]},{"given":"Rolf","family":"Ernst","sequence":"additional","affiliation":[{"name":"Technical University of Braunschweig"}]},{"given":"Enrico","family":"Billich","sequence":"additional","affiliation":[{"name":"Chemnitz University of Technology"}]},{"given":"Claudia","family":"Tischendorf","sequence":"additional","affiliation":[{"name":"Chemnitz University of Technology"}]},{"given":"Ulrich","family":"Heinkel","sequence":"additional","affiliation":[{"name":"Chemnitz University of Technology"}]},{"given":"Frank","family":"Ieromnimon","sequence":"additional","affiliation":[{"name":"Intracom Telecom Solutions S.A."}]},{"given":"Dimitrios","family":"Kritharidis","sequence":"additional","affiliation":[{"name":"Intracom Telecom Solutions S.A."}]},{"given":"Axel","family":"Schneider","sequence":"additional","affiliation":[{"name":"Alcatel-Lucent"}]},{"given":"Joachim","family":"Knaeblein","sequence":"additional","affiliation":[{"name":"Alcatel-Lucent"}]},{"given":"Wolfram","family":"Putzke-R\u00f6ming","sequence":"additional","affiliation":[{"name":"Deutsche Thomson OHG"}]}],"member":"320","published-online":{"date-parts":[[2013,4,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523070"},{"key":"e_1_2_1_2_1","unstructured":"Bertin P. Roncin D. and Vuillemin J. 1989. Introduction to Programmable Active Memories. Prentice Hall 300--309.   Bertin P. Roncin D. and Vuillemin J. 1989. Introduction to Programmable Active Memories. Prentice Hall 300--309."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403523"},{"volume-title":"Proceedings of the 4th International Workshop on Synthesis, Architectures, Modeling and Simulation (SAMOS). 293--302","author":"Cambonie J.","key":"e_1_2_1_4_1","unstructured":"Cambonie , J. , Gu\u00e9rin , S. , Keryell , R. , Lagadec , L. , Pottier , B. , Sentieys , O. , Weber , B. , and Yazdani , S . 2004. Compiler and system techniques for soc distributed reconfigurable accelerators . In Proceedings of the 4th International Workshop on Synthesis, Architectures, Modeling and Simulation (SAMOS). 293--302 . Cambonie, J., Gu\u00e9rin, S., Keryell, R., Lagadec, L., Pottier, B., Sentieys, O., Weber, B., and Yazdani, S. 2004. Compiler and system techniques for soc distributed reconfigurable accelerators. In Proceedings of the 4th International Workshop on Synthesis, Architectures, Modeling and Simulation (SAMOS). 293--302."},{"volume-title":"Proceedings of the Design Automation and Test in Europe (DATE).","author":"Campi F.","key":"e_1_2_1_5_1","unstructured":"Campi , F. , Deledda , A. , Pizzotti , M. , Ciccarelli , L. , Mucci , C. , Lodi , A. , Vanzolini , L. , and Vitkovski , A . 2007. Dynamically adaptive DSP for heterogeneous reconfigurable platforms . Proceedings of the Design Automation and Test in Europe (DATE). Campi, F., Deledda, A., Pizzotti, M., Ciccarelli, L., Mucci, C., Lodi, A., Vanzolini, L., and Vitkovski, A. 2007. Dynamically adaptive DSP for heterogeneous reconfigurable platforms. Proceedings of the Design Automation and Test in Europe (DATE)."},{"volume-title":"Proceedings of the International Solid State Circuits Conference.","author":"Campi F.","key":"e_1_2_1_6_1","unstructured":"Campi , F. , Toma , M. , Lodi , A. , Cappelli , A. , Canegallo , R. , and Guerrieri , R . 2003. A VLIW processor with reconfigurable instruction set for embedded applications . Proceedings of the International Solid State Circuits Conference. Campi, F., Toma, M., Lodi, A., Cappelli, A., Canegallo, R., and Guerrieri, R. 2003. A VLIW processor with reconfigurable instruction set for embedded applications. Proceedings of the International Solid State Circuits Conference."},{"key":"e_1_2_1_7_1","unstructured":"CRITICALBLUE 2005. Boosting software processing performance with coprocessor synthesis. White paper.  CRITICALBLUE 2005. Boosting software processing performance with coprocessor synthesis. White paper."},{"volume-title":"Proceedings of the IEEE Symposium on System on Chip (SoC'09)","author":"Coppola M.","key":"e_1_2_1_8_1","unstructured":"Coppola , M. , Locatelli , R. , Maruccia , G. , Pieralisi , L. , and Scandurra , A . 2004. Spidergron: A novel on-chip communication network . Proceedings of the IEEE Symposium on System on Chip (SoC'09) . Coppola, M., Locatelli, R., Maruccia, G., Pieralisi, L., and Scandurra, A. 2004. Spidergron: A novel on-chip communication network. Proceedings of the IEEE Symposium on System on Chip (SoC'09)."},{"volume-title":"Proceedings of the 12th Annual Symposium on Field-Programmable Custom Computing Machines (FCCM). 332--333","author":"Cappelli A.","key":"e_1_2_1_9_1","unstructured":"Cappelli , A. , Lodi , A. , Mucci , C. , Toma , M. , and Campi , F . 2004. A dataflow control unit for C-to-configurable pipelines compilation flow . Proceedings of the 12th Annual Symposium on Field-Programmable Custom Computing Machines (FCCM). 332--333 . Cappelli, A., Lodi, A., Mucci, C., Toma, M., and Campi, F. 2004. A dataflow control unit for C-to-configurable pipelines compilation flow. Proceedings of the 12th Annual Symposium on Field-Programmable Custom Computing Machines (FCCM). 332--333."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/508352.508353"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.839320"},{"key":"e_1_2_1_12_1","doi-asserted-by":"crossref","unstructured":"DeHon A. etal 2006. Stream computations organized for reconfigurable execution. Microprocessors and microsystems 30 6 334--354 Special Issue on FPGAs.  DeHon A. et al. 2006. Stream computations organized for reconfigurable execution. Microprocessors and microsystems 30 6 334--354 Special Issue on FPGAs.","DOI":"10.1016\/j.micpro.2006.02.009"},{"volume-title":"Proceedings of Design, Automation and Test in Europe (DATE). 194--199","author":"Do Carmo L., A.","key":"e_1_2_1_13_1","unstructured":"Do Carmo , L., A. , Heithecker , S. , R\u00fcffer , P. , Ernst , R. , R\u00fcckert , H. , Wischermann , G. , Gebel , K. , Fach , R. , Hunther , W. , Eichner , S. , and Scheller , G . 2006. A reconfigurable hardware\/software platform for computation intensive high-resolution real-time digital film applications . In Proceedings of Design, Automation and Test in Europe (DATE). 194--199 . Do Carmo, L., A., Heithecker, S., R\u00fcffer, P., Ernst, R., R\u00fcckert, H., Wischermann, G., Gebel, K., Fach, R., Hunther, W., Eichner, S., and Scheller, G. 2006. A reconfigurable hardware\/software platform for computation intensive high-resolution real-time digital film applications. In Proceedings of Design, Automation and Test in Europe (DATE). 194--199."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.953269"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1460361.1460365"},{"volume-title":"Proceedings of the SMPTE Technical Conference.","author":"Eichner S.","key":"e_1_2_1_16_1","unstructured":"Eichner , S. , Scheller , G. , Wessely , U. , R\u00fcckert , H. , and Hedtke , R . 2005. Motion compensated spatial-temporal reduction of film grain noise in the wavelet domain . In Proceedings of the SMPTE Technical Conference. Eichner, S., Scheller, G., Wessely, U., R\u00fcckert, H., and Hedtke, R. 2005. Motion compensated spatial-temporal reduction of film grain noise in the wavelet domain. In Proceedings of the SMPTE Technical Conference."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339682"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300982"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5555\/367072.367839"},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the Anniversary Colloquium at Prof. Glesner's 60s Birthday.","author":"Hartenstein R.","year":"2003","unstructured":"Hartenstein , R. 2003 . Rekonfigurable computing: Paradigmen-Wechsel ersch\u00fcttern die fundamente der informatik . Proceedings of the Anniversary Colloquium at Prof. Glesner's 60s Birthday. Hartenstein, R. 2003. Rekonfigurable computing: Paradigmen-Wechsel ersch\u00fcttern die fundamente der informatik. Proceedings of the Anniversary Colloquium at Prof. Glesner's 60s Birthday."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/549928.795741"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2008.150"},{"volume-title":"Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP'88)","author":"Le Gall D.","key":"e_1_2_1_23_1","unstructured":"Le Gall D. and Tabatabai , A . 1988. Sub-band coding of digital images using symmetric short kernel filters and arithmetic coding techniques . In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP'88) . 761--764. Le Gall D. and Tabatabai, A. 1988. Sub-band coding of digital images using symmetric short kernel filters and arithmetic coding techniques. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP'88). 761--764."},{"volume-title":"Proceedings of the 3rd International Workshop on Synthesis, Architectures, Modeling and Simulation (SAMOS).","author":"Lenormand E.","key":"e_1_2_1_24_1","unstructured":"Lenormand , E. and Edelin , G . 2003. An industrial perspective: Pragmatic high-end signal processing environment at Thales . In Proceedings of the 3rd International Workshop on Synthesis, Architectures, Modeling and Simulation (SAMOS). Lenormand, E. and Edelin, G. 2003. An industrial perspective: Pragmatic high-end signal processing environment at Thales. In Proceedings of the 3rd International Workshop on Synthesis, Architectures, Modeling and Simulation (SAMOS)."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.31"},{"volume-title":"Proceedings of 14th International Conference on Fleld-Programmable Logic and Applications (FPL). 434--443","author":"Moscu Panainte E.","key":"e_1_2_1_26_1","unstructured":"Moscu Panainte , E. , Bertels , K. , and Vassiliadis , S . 2004. The PowerPC Backend Molen Compiler . In Proceedings of 14th International Conference on Fleld-Programmable Logic and Applications (FPL). 434--443 . Moscu Panainte, E., Bertels, K., and Vassiliadis, S. 2004. The PowerPC Backend Molen Compiler. In Proceedings of 14th International Conference on Fleld-Programmable Logic and Applications (FPL). 434--443."},{"volume-title":"Proceedings of ProRISC. 415--420","author":"Moscu Panainte E.","key":"e_1_2_1_27_1","unstructured":"Moscu Panainte , E. , Bertels , K. , and Vassiliadis , S . 2005a. FPGA-area allocation for partial run-time reconfiguration . Proceedings of ProRISC. 415--420 . Moscu Panainte, E., Bertels, K., and Vassiliadis, S. 2005a. FPGA-area allocation for partial run-time reconfiguration. Proceedings of ProRISC. 415--420."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.184"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1210268.1210274"},{"volume-title":"Proceedings of the International Symposium on Systems-on-Chip (SOC'03)","author":"Mucci C.","key":"e_1_2_1_30_1","unstructured":"Mucci , C. , Chiesa , C. , Lodi , A. , Toma , M. , and Campi , F . 2003. A C-based algorithm development flow for a reconfigurable processor architecture . In Proceedings of the International Symposium on Systems-on-Chip (SOC'03) . 69--73. Mucci, C., Chiesa, C., Lodi, A., Toma, M., and Campi, F. 2003. A C-based algorithm development flow for a reconfigurable processor architecture. In Proceedings of the International Symposium on Systems-on-Chip (SOC'03). 69--73."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358078"},{"key":"e_1_2_1_32_1","unstructured":"OMAP. http:\/\/www.ti.com.  OMAP. http:\/\/www.ti.com."},{"issue":"2","key":"e_1_2_1_33_1","first-page":"2005","article-title":"PACT Software Design System XPP-IIb (PSDS XPP-IIb) - Programming Tutorial","volume":"3","author":"Technologies","year":"2005","unstructured":"PACT XPP Technologies . 2005 . PACT Software Design System XPP-IIb (PSDS XPP-IIb) - Programming Tutorial . Version 3 . 2 , November 2005 . PACT XPP Technologies. 2005. PACT Software Design System XPP-IIb (PSDS XPP-IIb) - Programming Tutorial. Version 3.2, November 2005.","journal-title":"Version"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.5555\/874070.876043"},{"volume-title":"IEEE Custom Integrated Circuits Conference (CICC).","author":"Rossi D.","key":"e_1_2_1_35_1","unstructured":"Rossi , D. , Campi , F. , Deledda , A. , Spolzino , S. , and Pucillo , S . 2009. A heterogeneous digital signal processor implementation for dynamically reconfigurable computing . IEEE Custom Integrated Circuits Conference (CICC). Rossi, D., Campi, F., Deledda, A., Spolzino, S., and Pucillo, S. 2009. A heterogeneous digital signal processor implementation for dynamically reconfigurable computing. IEEE Custom Integrated Circuits Conference (CICC)."},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-2427-5_14"},{"volume-title":"Proceedings of the EDTC. 310","author":"Sanz C.","key":"e_1_2_1_37_1","unstructured":"Sanz , C. , Garrido , M. J. , and Meneses , J. M . 1996. VLSI architecture for motion estimation using the block-matching algorithm . In Proceedings of the EDTC. 310 . Sanz, C., Garrido, M. J., and Meneses, J. M. 1996. VLSI architecture for motion estimation using the block-matching algorithm. In Proceedings of the EDTC. 310."},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"volume-title":"Proceedings of the Field-Programmable Logic and Its Applications (FPL'04)","author":"Thomas A.","key":"e_1_2_1_39_1","unstructured":"Thomas , A. and Becker , J . 2004. Dynamic adaptive routing techniques in multigrain dynamic reconfigurable hardware architectures . Proceedings of the Field-Programmable Logic and Its Applications (FPL'04) . Thomas, A. and Becker, J. 2004. Dynamic adaptive routing techniques in multigrain dynamic reconfigurable hardware architectures. Proceedings of the Field-Programmable Logic and Its Applications (FPL'04)."},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2013772"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.104"},{"volume-title":"Proceedings of Parallel and Distributed Processing Symposium.","author":"Vorbach M.","key":"e_1_2_1_42_1","unstructured":"Vorbach , M. and Becker , J . 2003. Reconfigurable processor architectures for mobile phones . Proceedings of Parallel and Distributed Processing Symposium. Vorbach, M. and Becker, J. 2003. Reconfigurable processor architectures for mobile phones. Proceedings of Parallel and Distributed Processing Symposium."},{"volume-title":"Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS).","author":"Whitty S.","key":"e_1_2_1_43_1","unstructured":"Whitty , S. and Ernst , R . 2008. A bandwidth optimized SDRAM controller for the MORPHEUS reconfigurable architecture . In Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS). Whitty, S. and Ernst, R. 2008. A bandwidth optimized SDRAM controller for the MORPHEUS reconfigurable architecture. In Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS)."},{"volume-title":"Proceedings of Design, Automation and Test in Europe (DATE).","author":"Whitty S.","key":"e_1_2_1_44_1","unstructured":"Whitty , S. , Sahlbach , H. , Putzke-R\u00f6ming , W. , and Ernst , R . 2009. Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture . In Proceedings of Design, Automation and Test in Europe (DATE). Whitty, S., Sahlbach, H., Putzke-R\u00f6ming, W., and Ernst, R. 2009. Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture. In Proceedings of Design, Automation and Test in Europe (DATE)."},{"volume-title":"Proceedings of Design, Automation and Test in Europe (DATE).","author":"Whitty S.","key":"e_1_2_1_45_1","unstructured":"Whitty , S. , Sahlbach , H. , Hurlburt , B. , Putzke-R\u00f6ming , W. , and Ernst , R . 2010. Application-specific memory performance of a heterogeneous reconfigurable architecture . In Proceedings of Design, Automation and Test in Europe (DATE). Whitty, S., Sahlbach, H., Hurlburt, B., Putzke-R\u00f6ming, W., and Ernst, R. 2010. Application-specific memory performance of a heterogeneous reconfigurable architecture. In Proceedings of Design, Automation and Test in Europe (DATE)."},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/113445.113449"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2442116.2442120","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2442116.2442120","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:19:06Z","timestamp":1750234746000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2442116.2442120"}},"subtitle":["A heterogeneous dynamically reconfigurable platform for designing highly complex embedded systems"],"short-title":[],"issued":{"date-parts":[[2013,3,10]]},"references-count":46,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2013,3,10]]}},"alternative-id":["10.1145\/2442116.2442120"],"URL":"https:\/\/doi.org\/10.1145\/2442116.2442120","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2013,3,10]]},"assertion":[{"value":"2010-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-04-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}