{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,4]],"date-time":"2026-05-04T10:10:08Z","timestamp":1777889408072,"version":"3.51.4"},"reference-count":34,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2013,3,10]],"date-time":"2013-03-10T00:00:00Z","timestamp":1362873600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Chinese Academy of Sciences Comprehensive Strategic Cooperation Projects in Guangdong Province"},{"DOI":"10.13039\/501100002920","name":"Research Grants Council, University Grants Committee, Hong Kong","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002920","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2013,3,10]]},"abstract":"<jats:p>About 55% of all CPUs sold in the world are 8-bit microcontrollers or microprocessors which can only access limited memory space without extending address buses. Partitioned memory with bank switching is a technique to increase memory size without extending address buses. Bank Selection Instructions (BSLs) need to be inserted into the original programs to modify the bank register to point to the desired banks. These BSLs introduce both code size and execution time overheads. In this paper, we partition variables into different banks and insert BSLs at different positions of programs so that the overheads can be minimized. Minimizing speed (execution time) overhead and minimizing space (code size) overhead are two objectives investigated in this paper. A multi-copy approach is also proposed to store multiple copies of several variables on different banks when the memory space allows. It takes the read\/write properties of variables into consideration and achieves more BSL overhead reduction. Experiments show that the proposed algorithms can reduce BSL overheads effectively compared to state-of-the-art techniques.<\/jats:p>","DOI":"10.1145\/2442116.2442126","type":"journal-article","created":{"date-parts":[[2013,4,9]],"date-time":"2013-04-09T12:17:58Z","timestamp":1365509878000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Joint variable partitioning and bank selection instruction optimization for partitioned memory architectures"],"prefix":"10.1145","volume":"12","author":[{"given":"Tiantian","family":"Liu","sequence":"first","affiliation":[{"name":"City University of Hong Kong and Cloud Computing Center, Chinese Academy of Sciences, Hong Kong SAR, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chun Jason","family":"Xue","sequence":"additional","affiliation":[{"name":"City University of Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Minming","family":"Li","sequence":"additional","affiliation":[{"name":"City University of Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,4,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1007912.1007931"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the Algorithms and Data Structures Symposium (WADS'11)","author":"Calinescu G.","unstructured":"Calinescu , G. and Li , M . 2011. Register loading via linear programming . In Proceedings of the Algorithms and Data Structures Symposium (WADS'11) . Calinescu, G. and Li, M. 2011. Register loading via linear programming. In Proceedings of the Algorithms and Data Structures Symposium (WADS'11)."},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the 25th Annual International Symposium on Microarchitecture. 292--300","author":"Capitanio A.","unstructured":"Capitanio , A. , Dutt , N. , and Nicolau , A . 1992. Partitioned register files for vliws: A preliminary analysis of tradeoffs . In Proceedings of the 25th Annual International Symposium on Microarchitecture. 292--300 . Capitanio, A., Dutt, N., and Nicolau, A. 1992. Partitioned register files for vliws: A preliminary analysis of tradeoffs. In Proceedings of the 25th Annual International Symposium on Microarchitecture. 292--300."},{"key":"e_1_2_1_4_1","volume-title":"Graph Transformation: Applications, Languages and Tools. World Scientific.","author":"Ehrig H.","year":"1997","unstructured":"Ehrig , H. , Engels , G. , and Kreowski , H. J . 1997 . Handbook of Graph Grammars and Computing by Graph Transformation: Applications, Languages and Tools. World Scientific. Ehrig, H., Engels, G., and Kreowski, H. J. 1997. Handbook of Graph Grammars and Computing by Graph Transformation: Applications, Languages and Tools. World Scientific."},{"key":"e_1_2_1_5_1","unstructured":"Freescale68HC11E. 2005. http:\/\/cache.freescale.com\/files\/microcontrollers\/doc\/data_sheet\/M68HC11E.pdf. Freescale68HC11E. 2005. http:\/\/cache.freescale.com\/files\/microcontrollers\/doc\/data_sheet\/M68HC11E.pdf."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/1128020.1128563"},{"key":"e_1_2_1_7_1","unstructured":"Haier. 2011. Hr6p90\/90h\/91\/91h\/92\/92h data sheet. http:\/\/www.ichaier.com\/uploadfile\/2011\/0412\/20110412035633586.pdf. Haier. 2011. Hr6p90\/90h\/91\/91h\/92\/92h data sheet. http:\/\/www.ichaier.com\/uploadfile\/2011\/0412\/20110412035633586.pdf."},{"key":"e_1_2_1_8_1","volume-title":"Lecture Notes In Computer Science","volume":"2304","author":"Kandemir M. T.","unstructured":"Kandemir , M. T. , Kolcu , I. , and Kadayif , I . 2002. Influence of loop optimizations on energy consumption of multi-bank memory systems . Lecture Notes In Computer Science , vol. 2304 , Springer, Berlin, 276--292. Kandemir, M. T., Kolcu, I., and Kadayif, I. 2002. Influence of loop optimizations on energy consumption of multi-bank memory systems. Lecture Notes In Computer Science, vol. 2304, Springer, Berlin, 276--292."},{"key":"e_1_2_1_9_1","volume-title":"Metis: A hypergraph partitioning package version 5.0","author":"Karypis G.","year":"2011","unstructured":"Karypis , G. and Kumar , V . 2011 . Metis: A hypergraph partitioning package version 5.0 . http:\/\/www.cs. unn.edu\/nmetis. Karypis, G. and Kumar, V. 2011. Metis: A hypergraph partitioning package version 5.0. http:\/\/www.cs. unn.edu\/nmetis."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.32"},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the 9th Annual ACM-SIAM Symposium on Discrete Algorithms. 942--949","author":"Krauthgamer R.","unstructured":"Krauthgamer , R. , Naor , J. S. , and Schwartz , R . 2009. Partitioning graphs into balanced components . In Proceedings of the 9th Annual ACM-SIAM Symposium on Discrete Algorithms. 942--949 . Krauthgamer, R., Naor, J. S., and Schwartz, R. 2009. Partitioning graphs into balanced components. In Proceedings of the 9th Annual ACM-SIAM Symposium on Discrete Algorithms. 942--949."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/CSE.2009.358"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2007.66"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1755888.1755890"},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASPDAC'10)","author":"Liu T.","unstructured":"Liu , T. , Li , M. , and Xue , C. J . 2010. Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks . In Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASPDAC'10) . 113--118. Liu, T., Li, M., and Xue, C. J. 2010. Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks. In Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASPDAC'10). 113--118."},{"key":"e_1_2_1_16_1","doi-asserted-by":"crossref","unstructured":"MiBench. 2002. http:\/\/www.eecs.umich.edu\/mibench\/. MiBench. 2002. http:\/\/www.eecs.umich.edu\/mibench\/.","DOI":"10.1145\/504689.504690"},{"key":"e_1_2_1_17_1","unstructured":"MOS6502. 1976. Mos mcs6500 family programming manual. http:\/\/archive.6502.org\/books\/mcs6500_family_programming_manual.pdf. MOS6502. 1976. Mos mcs6500 family programming manual. http:\/\/archive.6502.org\/books\/mcs6500_family_programming_manual.pdf."},{"key":"e_1_2_1_18_1","volume-title":"Tech. Rep. ECE-CE-2010-2","author":"Patney A.","year":"2010","unstructured":"Patney , A. , Tarjan , D. , Owens , J. D. , and Dally , W. J . 2010 . Architecture and compilation for large, multi-banked register files. Tech. Rep. ECE-CE-2010-2 , University of California, Davis . http:\/\/idav. ucdavis.edu\/&sim;anjul\/aligned-reg10-techreport.pdf. Patney, A., Tarjan, D., Owens, J. D., and Dally, W. J. 2010. Architecture and compilation for large, multi-banked register files. Tech. Rep. ECE-CE-2010-2, University of California, Davis. http:\/\/idav. ucdavis.edu\/&sim;anjul\/aligned-reg10-techreport.pdf."},{"key":"e_1_2_1_19_1","volume-title":"Embedded Controller FORTH for the 8051 Family","author":"Payne W. H.","unstructured":"Payne , W. H. 1990. Embedded Controller FORTH for the 8051 Family . Academic Press , Boston, MA . Payne, W. H. 1990. Embedded Controller FORTH for the 8051 Family. Academic Press, Boston, MA."},{"key":"e_1_2_1_20_1","unstructured":"PIC16F877A. 2003. http:\/\/ww1.microchip.com\/downloads\/en\/devicedoc\/39582b.pdf. PIC16F877A. 2003. http:\/\/ww1.microchip.com\/downloads\/en\/devicedoc\/39582b.pdf."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555760"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237193"},{"key":"e_1_2_1_23_1","unstructured":"Samsung Corp. 1999. Calmrisc8 specification. Samsung Corp. 1999. Calmrisc8 specification."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1176760.1176786"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1331331.1331336"},{"key":"e_1_2_1_26_1","unstructured":"SimpleScalar. 2008. http:\/\/www.simplescalar.com\/. SimpleScalar. 2008. http:\/\/www.simplescalar.com\/."},{"key":"e_1_2_1_27_1","unstructured":"Technology Inc. Microchip. 2008. Hi-tech for pic10\/12\/16 users guide. http:\/\/ww1.microchip.com\/downloads\/en\/DeviceDoc\/manual_9_71.pdf. Technology Inc. Microchip. 2008. Hi-tech for pic10\/12\/16 users guide. http:\/\/ww1.microchip.com\/downloads\/en\/DeviceDoc\/manual_9_71.pdf."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1059876.1059885"},{"key":"e_1_2_1_29_1","volume-title":"Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing. 1453--1457","author":"Xue C. J.","unstructured":"Xue , C. J. , Liu , T. , Shao , Z. , and et al, J. H. 2008. Address assignment sensitive variable partitioning and scheduling for dsps with multiple memory banks . In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing. 1453--1457 . Xue, C. J., Liu, T., Shao, Z., and et al, J. H. 2008. Address assignment sensitive variable partitioning and scheduling for dsps with multiple memory banks. In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing. 1453--1457."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICESS.2008.66"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1007\/11572961_22"},{"key":"e_1_2_1_32_1","volume-title":"Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS'02)","author":"Zhuge Q.","unstructured":"Zhuge , Q. , Xiao , B. , and Sha , E. H . -M. 2002. Variable partitioning and scheduling of multiple memory architectures for dsp . In Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS'02) . 332--339. Zhuge, Q., Xiao, B., and Sha, E. H.-M. 2002. Variable partitioning and scheduling of multiple memory architectures for dsp. In Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS'02). 332--339."},{"key":"e_1_2_1_33_1","unstructured":"Zilog. 2004. http:\/\/www.zilog.com\/docs\/z80\/um0080.pdf. Zilog. 2004. http:\/\/www.zilog.com\/docs\/z80\/um0080.pdf."},{"key":"e_1_2_1_34_1","volume-title":"Proceedings of the International Conference on Signal Processing and Technology (ICSPAT'94)","author":"Zivojnovic V.","unstructured":"Zivojnovic , V. , Martinez , J. , Schl\u00e4ger , C. , and Meyr , H . 1994. Dspstone: A dsp-oriented benchmarking methodology . In Proceedings of the International Conference on Signal Processing and Technology (ICSPAT'94) . 715--722. Zivojnovic, V., Martinez, J., Schl\u00e4ger, C., and Meyr, H. 1994. Dspstone: A dsp-oriented benchmarking methodology. In Proceedings of the International Conference on Signal Processing and Technology (ICSPAT'94). 715--722."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2442116.2442126","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2442116.2442126","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:19:06Z","timestamp":1750234746000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2442116.2442126"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3,10]]},"references-count":34,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2013,3,10]]}},"alternative-id":["10.1145\/2442116.2442126"],"URL":"https:\/\/doi.org\/10.1145\/2442116.2442126","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,3,10]]},"assertion":[{"value":"2011-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-11-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-04-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}