{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,14]],"date-time":"2026-05-14T00:05:42Z","timestamp":1778717142412,"version":"3.51.4"},"reference-count":62,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2013,3,10]],"date-time":"2013-03-10T00:00:00Z","timestamp":1362873600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000144","name":"Division of Computer and Network Systems","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000144","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002920","name":"Research Grants Council, University Grants Committee, Hong Kong","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002920","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2013,3,10]]},"abstract":"<jats:p>Recent advances in circuit and semiconductor technologies have pushed Non-Volatile Memory (NVM) technologies into a new era. These technologies exhibit appealing properties such as low power consumption, non-volatility, shock-resistivity, and high density. However, there are challenges to which we need answers in the road of applying non-volatile memories as main memory in embedded computer systems. First, when compared with DRAM, NVMs have a limited number of write\/erase cycles. Second, write activities on NVM are more expensive than DRAM memory in terms of energy consumption and access latency. Both challenges will benefit from the reduction of the write activities on the NVMs.<\/jats:p>\n          <jats:p>In this paper, we target embedded Chip Multiprocessors (CMPs) with Scratch Pad Memory (SPM) and non-volatile main memory. We introduce scheduling, data migration, and recomputation techniques to reduce the number of write activities on NVMs. Experimental results show that the proposed methods can reduce the number of writes by 58.46% on average, which means that the NVM can last 2.8 times as long as before. For Phase Change Memory (PCM), the lifetime is extended from 2.5 years to about 7 years on average and 15 years at the most. Also, the finish time of the tested programs is reduced by an average of 38.07%, and the energy consumption is reduced by an average of 51.23%.<\/jats:p>","DOI":"10.1145\/2442116.2442127","type":"journal-article","created":{"date-parts":[[2013,4,9]],"date-time":"2013-04-09T12:17:58Z","timestamp":1365509878000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":38,"title":["Write activity reduction on non-volatile main memories for embedded chip multiprocessors"],"prefix":"10.1145","volume":"12","author":[{"given":"Jingtong","family":"Hu","sequence":"first","affiliation":[{"name":"University of Texas at Dallas, Richardson, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chun Jason","family":"Xue","sequence":"additional","affiliation":[{"name":"City University of Hong Kong, Kowloon, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qingfeng","family":"Zhuge","sequence":"additional","affiliation":[{"name":"Chongqing University, Chongqing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei-Che","family":"Tseng","sequence":"additional","affiliation":[{"name":"University of Texas at Dallas, Richardson, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Edwin H.-M.","family":"Sha","sequence":"additional","affiliation":[{"name":"Chongqing University and University of Texas at Dallas, Chongqing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,4,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630103"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/774789.774805"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.21"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278533"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630130"},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe (DATE'06)","author":"Chen G.","unstructured":"Chen , G. , Ozturk , O. , Kandemir , M. , and Karakoy , M . 2006. Dynamic scratch-pad memory management for irregular array access patterns . In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'06) . 931--936. Chen, G., Ozturk, O., Kandemir, M., and Karakoy, M. 2006. Dynamic scratch-pad memory management for irregular array access patterns. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'06). 931--936."},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the International Symposium on Quality Electronic Design (ISQED'08)","author":"Chen Y.","unstructured":"Chen , Y. , Wang , X. , Li , H. , Liu , H. , and Dimitrov , D . 2008. Design margin exploration of spin-torque transfer ram (spram) . In Proceedings of the International Symposium on Quality Electronic Design (ISQED'08) . 684--690. Chen, Y., Wang, X., Li, H., Liu, H., and Dimitrov, D. 2008. Design margin exploration of spin-torque transfer ram (spram). In Proceedings of the International Symposium on Quality Electronic Design (ISQED'08). 684--690."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630086"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687449"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391610"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454144"},{"key":"e_1_2_1_12_1","volume-title":"Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'10)","author":"Ferreira A. P.","unstructured":"Ferreira , A. P. , Zhou , M. , Bock , S. , Childers , B. , Melhem , R. , and Mosse , D . 2010. Increasing pcm main memory lifetime . In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'10) . 914--919. Ferreira, A. P., Zhou, M., Bock, S., Childers, B., Melhem, R., and Mosse, D. 2010. Increasing pcm main memory lifetime. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'10). 914--919."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/28869.28874"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.26"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2097307"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837363"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2010.5521139"},{"key":"e_1_2_1_18_1","volume-title":"Proceedings of the Design, Automation and Test in Europe Conference and Exhibition.","author":"Hu J.","unstructured":"Hu , J. , Xue , C. J. , Zhuge , Q. , Tseng , W.-C. , and Sha , E. H . -M. 2011b. Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory . In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. Hu, J., Xue, C. J., Zhuge, Q., Tseng, W.-C., and Sha, E. H.-M. 2011b. Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition."},{"key":"e_1_2_1_19_1","volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'11)","author":"Huang Y.","unstructured":"Huang , Y. , Liu , T. , and Xue , C . 2011. Register allocation for write activity minimization on non-volatile main memory . In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'11) . Huang, Y., Liu, T., and Xue, C. 2011. Register allocation for write activity minimization on non-volatile main memory. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'11)."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1176254.1176310"},{"key":"e_1_2_1_21_1","volume-title":"Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'10)","author":"Joo Y.","unstructured":"Joo , Y. , Niu , D. , Dong , X. , Sun , G. , Chang , N. , and Xie , Y . 2010. Energy- and endurance-aware design of phase change memory caches . In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'10) . 136--141. Joo, Y., Niu, D., Dong, X., Sun, G., Chang, N., and Xie, Y. 2010. Energy- and endurance-aware design of phase change memory caches. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'10). 136--141."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1121013"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.514077"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/500001.500004"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.513974"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379049"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.822123"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.820866"},{"key":"e_1_2_1_29_1","unstructured":"Kanellos M. 2007. Ibm changes directions in magnetic memory. http:\/\/news.cnet.com\/IBM-changes-directions-in-magnetic-memory\/2100-1004_3-6203198.  Kanellos M. 2007. Ibm changes directions in magnetic memory. http:\/\/news.cnet.com\/IBM-changes-directions-in-magnetic-memory\/2100-1004_3-6203198."},{"key":"e_1_2_1_30_1","volume-title":"Proceedings of the Symposium on VLSI Technology. 98--99","author":"Kang D.-H.","unstructured":"Kang , D.-H. , Lee , J.-H. , Kong , J. , Ha , D. , Yu , J. , Um , C. , Park , J. , Yeung , F. , Kim , J. , Park , W. , Jeon , Y. , Lee , M. , Song , Y. , Oh , J. , Jeong , G. , and Jeong , H . 2008. Two-bit cell operation in diode-switch phase change memory cells with 90nm technology . In Proceedings of the Symposium on VLSI Technology. 98--99 . Kang, D.-H., Lee, J.-H., Kong, J., Ha, D., Yu, J., Um, C., Park, J., Yeung, F., Kim, J., Park, W., Jeon, Y., Lee, M., Song, Y., Oh, J., Jeong, G., and Jeong, H. 2008. Two-bit cell operation in diode-switch phase change memory cells with 90nm technology. In Proceedings of the Symposium on VLSI Technology. 98--99."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278535"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_2_1_33_1","volume-title":"Proceedings of the 30th Annual ACM\/IEEE International Symposium on Microarchitecture (MICRO'97)","author":"Lee C.","unstructured":"Lee , C. , Potkonjak , M. , and Mangione-Smith , W. H . 1997. Mediabench: A tool for evaluating and synthesizing multimedia and communicatons systems . In Proceedings of the 30th Annual ACM\/IEEE International Symposium on Microarchitecture (MICRO'97) . 330--335. Lee, C., Potkonjak, M., and Mangione-Smith, W. H. 1997. Mediabench: A tool for evaluating and synthesizing multimedia and communicatons systems. In Proceedings of the 30th Annual ACM\/IEEE International Symposium on Microarchitecture (MICRO'97). 330--335."},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1450135.1450144"},{"key":"e_1_2_1_35_1","volume-title":"Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'09)","author":"Li H.","unstructured":"Li , H. and Chen , Y . 2009. An overview of non-volatile memory technology and the implication for tools and architectures . In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'09) . 731--736. Li, H. and Chen, Y. 2009. An overview of non-volatile memory technology and the implication for tools and architectures. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'09). 731--736."},{"key":"e_1_2_1_36_1","volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'09)","author":"Li J.","unstructured":"Li , J. , Ndai , P. , Goel , A. , Liu , H. , and Roy , K . 2009. An alternate design paradigm for robust spin-torque transfer magnetic ram (stt mram) from circuit\/architecture perspective . In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'09) . 841--846. Li, J., Ndai, P., Goel, A., Liu, H., and Roy, K. 2009. An alternate design paradigm for robust spin-torque transfer magnetic ram (stt mram) from circuit\/architecture perspective. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'09). 841--846."},{"key":"e_1_2_1_37_1","volume-title":"Proceedings of the 27th Annual Hawaii International Conference on System Sciences.","author":"Liao G.","year":"1994","unstructured":"Liao , G. 1994 . A comparative study of dsp multiprocessor list scheduling heuristics . In Proceedings of the 27th Annual Hawaii International Conference on System Sciences. Liao, G. 1994. A comparative study of dsp multiprocessor list scheduling heuristics. In Proceedings of the 27th Annual Hawaii International Conference on System Sciences."},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024819"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1366110.1366204"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.115"},{"key":"e_1_2_1_41_1","volume-title":"Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED'08)","author":"Ozturk O.","unstructured":"Ozturk , O. , Kandemir , M. , and Narayanan , S. H. K. 2008. A scratch-pad memory aware dynamic loop scheduling algorithm . In Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED'08) . 738--743. Ozturk, O., Kandemir, M., and Narayanan, S. H. K. 2008. A scratch-pad memory aware dynamic loop scheduling algorithm. In Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED'08). 738--743."},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1017753.1017775"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/944645.944684"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454140"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/1176760.1176789"},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"e_1_2_1_47_1","volume-title":"Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'09)","author":"Roberts D.","unstructured":"Roberts , D. , Kgil , T. , and Mudge , T. N . 2009. Using non-volatile memory to save energy in servers . In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'09) . 743--748. Roberts, D., Kgil, T., and Mudge, T. N. 2009. Using non-volatile memory to save energy in servers. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'09). 743--748."},{"key":"e_1_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785503"},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2005.45"},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/1176760.1176809"},{"key":"e_1_2_1_51_1","volume-title":"-M","author":"Tseng W.-C.","year":"2010","unstructured":"Tseng , W.-C. , Xue , C. J. , Zhuge , Q. , Hu , J. , and Sha , E. H . -M . 2010 . Optimal scheduling to minimize non-volatile memory access time with hardware cache. In Proceedings of the VLSI-SOC '10. 131--136. Tseng, W.-C., Xue, C. J., Zhuge, Q., Hu, J., and Sha, E. H.-M. 2010. Optimal scheduling to minimize non-volatile memory access time with hardware cache. In Proceedings of the VLSI-SOC'10. 131--136."},{"key":"e_1_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/951710.951747"},{"key":"e_1_2_1_53_1","unstructured":"Williams I. 2009. Phase change memory is another step closer. http:\/\/www.hpcwire.com\/news\/Phase-Change-Memory-is-Another-Step-Closer.html.  Williams I. 2009. Phase change memory is another step closer. http:\/\/www.hpcwire.com\/news\/Phase-Change-Memory-is-Another-Step-Closer.html."},{"key":"e_1_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195506"},{"key":"e_1_2_1_55_1","volume-title":"-W","author":"Wu P.-L.","year":"2009","unstructured":"Wu , P.-L. , Chang , Y.-H. , and Kuo , T . -W . 2009 . A file-system-aware ftl design for flash-memory storage systems. In Proceedings of the ACM\/IEEE Design, Automation and Test in Europe (DATE '09). 393--398. Wu, P.-L., Chang, Y.-H., and Kuo, T.-W. 2009. A file-system-aware ftl design for flash-memory storage systems. In Proceedings of the ACM\/IEEE Design, Automation and Test in Europe (DATE'09). 393--398."},{"key":"e_1_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555761"},{"key":"e_1_2_1_57_1","volume-title":"Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'09)","author":"Wu X.","unstructured":"Wu , X. , Li , J. , Zhang , L. , Speight , E. , and Xie , Y . 2009. Power and performance of read-write aware hybrid caches with non-volatile memories . In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'09) . 737--742. Wu, X., Li, J., Zhang, L., Speight, E., and Xie, Y. 2009. Power and performance of read-write aware hybrid caches with non-volatile memories. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'09). 737--742."},{"key":"e_1_2_1_58_1","doi-asserted-by":"crossref","unstructured":"Yeung F. and etal 2005. ge2sb2te5 confined structures and integration of 64mb phase-change random access memory. Japanese Journal of Applied Physics 2691--2695.  Yeung F. and et al. 2005. ge 2 sb 2 te 5 confined structures and integration of 64mb phase-change random access memory. Japanese Journal of Applied Physics 2691--2695.","DOI":"10.1143\/JJAP.44.2691"},{"key":"e_1_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.30"},{"key":"e_1_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"},{"key":"e_1_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"e_1_2_1_62_1","volume-title":"Dspstone: A dsp-oriented benchmarking methodology. Tech. rep.","author":"Zivojnovic V.","year":"1994","unstructured":"Zivojnovic , V. , Martinez , J. , Schlager , C. , and Meyr , H . 1994 . Dspstone: A dsp-oriented benchmarking methodology. Tech. rep. , Aachen Univeristy , Aachen, Germany . Zivojnovic, V., Martinez, J., Schlager, C., and Meyr, H. 1994. Dspstone: A dsp-oriented benchmarking methodology. Tech. rep., Aachen Univeristy, Aachen, Germany."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2442116.2442127","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2442116.2442127","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:19:06Z","timestamp":1750234746000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2442116.2442127"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3,10]]},"references-count":62,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2013,3,10]]}},"alternative-id":["10.1145\/2442116.2442127"],"URL":"https:\/\/doi.org\/10.1145\/2442116.2442127","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,3,10]]},"assertion":[{"value":"2011-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-10-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-04-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}