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Multi-core processors are an answer to these demands, however task interferences make multi-cores more difficult to analyze from a worst-case execution time point of view than single-core processors. We propose a multi-core SMT processor that ensures a bounded maximum delay a task can suffer due to inter-task interferences. Multiple hard real-time tasks can be executed on different cores together with additional non real-time tasks. Our evaluation shows that the proposed MERASA multi-core provides predictability for hard real-time tasks and also high performance for non hard real-time tasks.<\/jats:p>","DOI":"10.1145\/2442116.2442129","type":"journal-article","created":{"date-parts":[[2013,4,9]],"date-time":"2013-04-09T12:17:58Z","timestamp":1365509878000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":17,"title":["A hard real-time capable multi-core SMT processor"],"prefix":"10.1145","volume":"12","author":[{"given":"Marco","family":"Paolieri","sequence":"first","affiliation":[{"name":"Barcelona Supercomputing Center, Universitat Polit\u00e8cnica de Catalunya"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J\u00f6rg","family":"Mische","sequence":"additional","affiliation":[{"name":"University of Augsburg"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefan","family":"Metzlaff","sequence":"additional","affiliation":[{"name":"University of Augsburg"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mike","family":"Gerdes","sequence":"additional","affiliation":[{"name":"University of Augsburg"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eduardo","family":"Qui\u00f1ones","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sascha","family":"Uhrig","sequence":"additional","affiliation":[{"name":"Technical University of Dortmund"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Theo","family":"Ungerer","sequence":"additional","affiliation":[{"name":"University of Augsburg"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francisco J.","family":"Cazorla","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Spanish National Research Council"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,4,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.2008.33"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2008.42"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the European Congress on Embedded Real-Time Software (ERTS).","author":"Cass\u00e9 H.","unstructured":"Cass\u00e9 , H. and Sainrat , P . 2006. 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