{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:33:31Z","timestamp":1772724811074,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":46,"publisher":"ACM","license":[{"start":{"date-parts":[[2013,3,16]],"date-time":"2013-03-16T00:00:00Z","timestamp":1363392000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2013,3,16]]},"DOI":"10.1145\/2451116.2451118","type":"proceedings-article","created":{"date-parts":[[2013,3,19]],"date-time":"2013-03-19T09:34:53Z","timestamp":1363685693000},"page":"1-12","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["GPUDet"],"prefix":"10.1145","author":[{"given":"Hadi","family":"Jooybar","sequence":"first","affiliation":[{"name":"University of British Columbia, Vancouver, BC, Canada"}]},{"given":"Wilson W.L.","family":"Fung","sequence":"additional","affiliation":[{"name":"University of British Columbia, Vancouver, BC, Canada"}]},{"given":"Mike","family":"O'Connor","sequence":"additional","affiliation":[{"name":"mike.oconnor@amd.com, Austin, TX, USA"}]},{"given":"Joseph","family":"Devietti","sequence":"additional","affiliation":[{"name":"University of Washington, Seattle, WA, USA"}]},{"given":"Tor M.","family":"Aamodt","sequence":"additional","affiliation":[{"name":"University of British Columbia, Vancouver, BC, Canada"}]}],"member":"320","published-online":{"date-parts":[[2013,3,16]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"http:\/\/www.ece.ubc.ca\/~aamodt\/GPUDet.  http:\/\/www.ece.ubc.ca\/~aamodt\/GPUDet."},{"key":"e_1_3_2_1_2_1","unstructured":"White Paper | AMD Graphics Cores Next (GCN) Architecture. AMD June 2012.  White Paper | AMD Graphics Cores Next (GCN) Architecture. AMD June 2012."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2007.370254"},{"key":"e_1_3_2_1_4_1","volume-title":"OSDI","author":"Aviram A.","year":"2010","unstructured":"A. Aviram , S.-C. Weng , S. Hu , and B. Ford . Efficient system-enforced deterministic parallelism . In OSDI , 2010 . A. Aviram, S.-C. Weng, S. Hu, and B. Ford. Efficient system-enforced deterministic parallelism. In OSDI, 2010."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1735970.1736029"},{"key":"e_1_3_2_1_7_1","volume-title":"OSDI","author":"Bergan T.","year":"2010","unstructured":"T. Bergan , N. Hunt , L. Ceze , and S. D. Gribble . Deterministic Process Groups in dOS . In OSDI , 2010 . T. Bergan, N. Hunt, L. Ceze, and S. D. Gribble. Deterministic Process Groups in dOS. In OSDI, 2010."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2384616.2384625"},{"key":"e_1_3_2_1_9_1","volume-title":"NESL: A Nested Data-Parallel Language (Version 3.1). Technical report","author":"Blelloch G.","year":"2007","unstructured":"G. Blelloch . NESL: A Nested Data-Parallel Language (Version 3.1). Technical report , Carnegie Mellon University , Pittsburgh, PA , 2007 . G. Blelloch. NESL: A Nested Data-Parallel Language (Version 3.1). Technical report, Carnegie Mellon University, Pittsburgh, PA, 2007."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1640089.1640097"},{"key":"e_1_3_2_1_11_1","volume-title":"Automated Dynamic Analysis of CUDA Programs. In Third Workshop on Software Tools for MultiCore Systems","author":"Boyer M.","year":"2008","unstructured":"M. Boyer , K. Skadron , and W. Weimer . Automated Dynamic Analysis of CUDA Programs. In Third Workshop on Software Tools for MultiCore Systems , 2008 . M. Boyer, K. Skadron, and W. Weimer. Automated Dynamic Analysis of CUDA Programs. In Third Workshop on Software Tools for MultiCore Systems, 2008."},{"key":"e_1_3_2_1_12_1","volume-title":"Cloth in OpenCL","author":"Brownsword A.","year":"2009","unstructured":"A. Brownsword . Cloth in OpenCL , 2009 . A. Brownsword. Cloth in OpenCL, 2009."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1248648.1248652"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_3_2_1_15_1","volume-title":"United States Patent#7,353,369: System and Method for Managing Divergent Threads in a SIMD Architecture","author":"Coon B. W.","year":"2008","unstructured":"B. W. Coon United States Patent#7,353,369: System and Method for Managing Divergent Threads in a SIMD Architecture ( Assignee NVIDIA Corp .), April 2008 . B. W. Coon et al. United States Patent#7,353,369: System and Method for Managing Divergent Threads in a SIMD Architecture (Assignee NVIDIA Corp.), April 2008."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508255"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950376"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1086228.1086277"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155655"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.12"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/1782174.1782200"},{"key":"e_1_3_2_1_22_1","unstructured":"M. Hill and M. Xu. http:\/\/www.cs.wisc.edu\/ markhill\/racey.html 2009.  M. Hill and M. Xu. http:\/\/www.cs.wisc.edu\/ markhill\/racey.html 2009."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.5555\/2014698.2014870"},{"key":"e_1_3_2_1_24_1","unstructured":"Khronos Group. OpenCL. http:\/\/www.khronos.org\/opencl\/.  Khronos Group. OpenCL. http:\/\/www.khronos.org\/opencl\/."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2018323.2018337"},{"key":"e_1_3_2_1_26_1","volume-title":"United States Patent#8,086,806: Systems and methods for coalescing memory accesses of parallel threads","author":"Lars Nyland G. H.","year":"2011","unstructured":"G. H. Lars Nyland , John R. Nickolls and T. Mandal . United States Patent#8,086,806: Systems and methods for coalescing memory accesses of parallel threads ( Assignee NVIDIA Corp .), April 2011 . G. H. Lars Nyland, John R. Nickolls and T. Mandal. United States Patent#8,086,806: Systems and methods for coalescing memory accesses of parallel threads (Assignee NVIDIA Corp.), April 2011."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1810479.1810534"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1882291.1882320"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.31"},{"key":"e_1_3_2_1_30_1","volume-title":"ISCA","author":"Liu J.","year":"2012","unstructured":"J. Liu , B. Jaiyen , R. Veras , and O. Multu . RAIDR: Retention-Aware Intelligent DRAM Refresh . In ISCA , 2012 . J. Liu, B. Jaiyen, R. Veras, and O. Multu. RAIDR: Retention-Aware Intelligent DRAM Refresh. In ISCA, 2012."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/2043556.2043587"},{"key":"e_1_3_2_1_32_1","volume-title":"NVIDIA","author":"Compute Architecture CUDA","year":"2009","unstructured":"NVIDIA's Next Generation CUDA Compute Architecture : Fermi . NVIDIA , October 2009 . NVIDIA's Next Generation CUDA Compute Architecture: Fermi. NVIDIA, October 2009."},{"key":"e_1_3_2_1_33_1","unstructured":"NVIDIA CUDA Programming Guide v3.1. NVIDIA Corp. 2010.  NVIDIA CUDA Programming Guide v3.1. NVIDIA Corp. 2010."},{"key":"e_1_3_2_1_34_1","unstructured":"NVML API Reference Manual v3.295.45. NVIDIA Corp. 2012.  NVML API Reference Manual v3.295.45. NVIDIA Corp. 2012."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508256"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/291889.291893"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.24"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2006.19"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522351"},{"key":"e_1_3_2_1_40_1","volume-title":"Efficient Synchronization Primitives for GPUs. CoRR, abs\/1110.4623","author":"Stuart J. A.","year":"2011","unstructured":"J. A. Stuart and J. D. Owens . Efficient Synchronization Primitives for GPUs. CoRR, abs\/1110.4623 , 2011 . J. A. Stuart and J. D. Owens. Efficient Synchronization Primitives for GPUs. CoRR, abs\/1110.4623, 2011."},{"key":"e_1_3_2_1_41_1","volume-title":"StreamIt: A Language for Streaming Applications. In CC '02","author":"Thies W.","year":"2002","unstructured":"W. Thies , M. Karczmarek , and S. P. Amarasinghe . StreamIt: A Language for Streaming Applications. In CC '02 , 2002 . W. Thies, M. Karczmarek, and S. P. Amarasinghe. StreamIt: A Language for Streaming Applications. In CC '02, 2002."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065944.1065975"},{"key":"e_1_3_2_1_43_1","volume-title":"United States Patent#6,630,933: Method and Apparatus for Compression and Decompression of Z Data","author":"Van Hook T. J.","year":"2003","unstructured":"T. J. Van Hook . United States Patent#6,630,933: Method and Apparatus for Compression and Decompression of Z Data ( Assignee ATI Technologies Inc .), October 2003 . T. J. Van Hook. United States Patent#6,630,933: Method and Apparatus for Compression and Decompression of Z Data (Assignee ATI Technologies Inc.), October 2003."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910957"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2010.5452013"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/1941553.1941574"}],"event":{"name":"ASPLOS '13: Architectural Support for Programming Languages and Operating Systems","location":"Houston Texas USA","acronym":"ASPLOS '13","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2451116.2451118","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2451116.2451118","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:18:49Z","timestamp":1750220329000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2451116.2451118"}},"subtitle":["a deterministic GPU architecture"],"short-title":[],"issued":{"date-parts":[[2013,3,16]]},"references-count":46,"alternative-id":["10.1145\/2451116.2451118","10.1145\/2451116"],"URL":"https:\/\/doi.org\/10.1145\/2451116.2451118","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/2499368.2451118","asserted-by":"object"},{"id-type":"doi","id":"10.1145\/2490301.2451118","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2013,3,16]]},"assertion":[{"value":"2013-03-16","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}