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This article studies the implementation, for such accelerators, of the floating-point power function\n            <jats:italic>x<\/jats:italic>\n            <jats:sup>y<\/jats:sup>\n            as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floating-point multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.\n          <\/jats:p>","DOI":"10.1145\/2457443.2457447","type":"journal-article","created":{"date-parts":[[2013,5,7]],"date-time":"2013-05-07T20:51:42Z","timestamp":1367959902000},"page":"1-15","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Floating-Point Exponentiation Units for Reconfigurable Computing"],"prefix":"10.1145","volume":"6","author":[{"given":"Florent","family":"de Dinechin","sequence":"first","affiliation":[{"name":"\u00c9cole Normale Sup\u00e9rieure de Lyon"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pedro","family":"Echeverr\u00eda","sequence":"additional","affiliation":[{"name":"Universidad Polit\u00e9cnica de Madrid"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marisa","family":"L\u00f3pez-Vallejo","sequence":"additional","affiliation":[{"name":"Universidad Polit\u00e9cnica de Madrid"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bogdan","family":"Pasca","sequence":"additional","affiliation":[{"name":"\u00c9cole Normale Sup\u00e9rieure de Lyon"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,5]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Altera. 2008a. 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A library of parameterized floating-point modules and their use. In Proceedings of the 12th International Conference on Field Programmable Logic and Applications. Lecture Notes in Computer Science, vol. 2438. Springer, 657--666."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2006.41"},{"key":"e_1_2_1_6_1","volume-title":"RR2010-22","author":"de Dinechin F.","year":"2010","unstructured":"de Dinechin , F. 2010 . A flexible floating-point logarithm for reconfigurable computers. LIP res. rep . RR2010-22 , ENS-Lyon. de Dinechin, F. 2010. A flexible floating-point logarithm for reconfigurable computers. LIP res. rep. RR2010-22, ENS-Lyon."},{"volume-title":"Proceedings of the International Conference on Field Programmable Technologies. IEEE, 110--117","author":"de Dinechin F.","key":"e_1_2_1_7_1","unstructured":"de Dinechin , F. and Pasca , B . 2010. Floating-point exponential functions for DSP-enabled FPGAs . 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An FPGA-specific approach to floating point accumulation and sum-of-products. In Proceedings of the International Conference on Field Programmable Technologies. IEEE, 33--40."},{"volume-title":"Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures and Processors. IEEE.","author":"de Dinechin F.","key":"e_1_2_1_11_1","unstructured":"de Dinechin , F. , Joldes , M. , and Pasca , B . 2010a. Automatic generation of polynomial-based hardware architectures for function evaluation . In Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures and Processors. IEEE. de Dinechin, F., Joldes, M., and Pasca, B. 2010a. Automatic generation of polynomial-based hardware architectures for function evaluation. In Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures and Processors. 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