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This paper presents an FPGA-based Connect6 solver with two-level move refinement. The solver has the dedicated hardware to accelerate the move refinement by exploiting various parallelism with a systolic array, linear arrays, and multiple score-calculation units. Implementation with a low-end FPGA demonstrates that the accelerator allows the two-level move refinement in the FPGA-based solver running at 90 MHz to be 103695 and 414 times faster than equivalent software implementation with NIOS II soft processor on the FPGA and Intel Core i7 processor operating at 2.93 GHz, respectively.<\/jats:p>","DOI":"10.1145\/2460216.2460218","type":"journal-article","created":{"date-parts":[[2013,4,9]],"date-time":"2013-04-09T12:17:58Z","timestamp":1365509878000},"page":"4-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["FPGA-based Connect6 solver with hardware-accelerated move refinement"],"prefix":"10.1145","volume":"40","author":[{"given":"Kentaro","family":"Sano","sequence":"first","affiliation":[{"name":"Tohoku University, Sendai, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yoshiaki","family":"Kono","sequence":"additional","affiliation":[{"name":"Tohoku University, Sendai, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,3,25]]},"reference":[{"volume-title":"http:\/\/risujin.org\/connectk\/","year":"2012","key":"e_1_2_1_1_1","unstructured":"Connect-k. http:\/\/risujin.org\/connectk\/ , 2012 . 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