{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:21:27Z","timestamp":1750306887439,"version":"3.41.0"},"reference-count":15,"publisher":"Association for Computing Machinery (ACM)","issue":"5","license":[{"start":{"date-parts":[[2012,3,25]],"date-time":"2012-03-25T00:00:00Z","timestamp":1332633600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2012,12,25]]},"abstract":"<jats:p>To support dynamic applications, FPGAs will need to have a software operating system equivalent resource manager. An abstract FPGA architecture is the foundation to develop such an FPGA resource manager. Previous research projects work on the FPGA abstraction by abstracting the computing and\/or the communication resources. However, various constraints made their proposals practically less useful due to the performance and\/or the area overheads. We develop a low overhead abstract FPGA architecture that has the important features such as dynamically sized reconfigurable regions, deterministic communications among regions, clock network management and in-circuit debugging for regions. The architecture is demonstrated by implementing three applications on the Xilinx Virtex 5 FPGAs. We evaluate our work by comparing the area and performance overheads due to the abstractions between the abstracted and the non-abstracted applications. Experimental results show that additional resources required due to abstractions are found to be 6.4% on average. This is achieved with low overheads on the timing performance.<\/jats:p>","DOI":"10.1145\/2460216.2460222","type":"journal-article","created":{"date-parts":[[2013,4,9]],"date-time":"2013-04-09T12:17:58Z","timestamp":1365509878000},"page":"28-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A low overhead abstract architecture for FPGA resource management"],"prefix":"10.1145","volume":"40","author":[{"given":"Rizwan","family":"Syed","sequence":"first","affiliation":[{"name":"National University of Singapore, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yajun","family":"Ha","sequence":"additional","affiliation":[{"name":"National University of Singapore, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bharadwaj","family":"Veeravalli","sequence":"additional","affiliation":[{"name":"National University of Singapore, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,3,25]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.1028"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/1058426.1058887"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.99"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt:20060186"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70763"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-006-0017-6"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1596532.1596540"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.54"},{"key":"e_1_2_1_9_1","first-page":"153","volume-title":"Intl. Conf.","author":"Bobda C.","year":"2005"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2006.25"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.323"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1985.6312192"},{"key":"e_1_2_1_13_1","unstructured":"Xilinx XUPV5 User Guide. Xilinx Oct. 2008 no. UG347.  Xilinx XUPV5 User Guide. Xilinx Oct. 2008 no. UG347."},{"key":"e_1_2_1_14_1","doi-asserted-by":"crossref","unstructured":"K. Xu H.264\/AVC Baseline Decoder. OpenCores Oct. 2009.  K. Xu H.264\/AVC Baseline Decoder. OpenCores Oct. 2009.","DOI":"10.1155\/2009\/425173"},{"key":"e_1_2_1_15_1","unstructured":"Xilinx Fast Fourier Transform v7.1. Xili  Xilinx Fast Fourier Transform v7.1. Xili"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2460216.2460222","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2460216.2460222","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:18:46Z","timestamp":1750234726000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2460216.2460222"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,3,25]]},"references-count":15,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2012,12,25]]}},"alternative-id":["10.1145\/2460216.2460222"],"URL":"https:\/\/doi.org\/10.1145\/2460216.2460222","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2012,3,25]]},"assertion":[{"value":"2012-03-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}