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To support the high speed dynamic reconfiguration, optially reconfigurable gate arrays (ORGAs) have been developed up to now. An ORGA consists of a holographic memory, a laser array, and an optially reconfigurable gate array VLSI. The holographic memory can store many configuration contexts. In addition, its large bandwidth optical connection enables high speed reconfiguration. However, photodiode sensitivities of conventional ORGAs were not good. This paper therefore presents a newly fabriated 0.18\u03c0m CMOS process optially reconfigurable gate array VLSI chip with highly sensitive photociruits.<\/jats:p>","DOI":"10.1145\/2460216.2460231","type":"journal-article","created":{"date-parts":[[2013,4,9]],"date-time":"2013-04-09T12:17:58Z","timestamp":1365509878000},"page":"82-86","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["0.18 \u03bcm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI"],"prefix":"10.1145","volume":"40","author":[{"given":"Takahiro","family":"Watanabe","sequence":"first","affiliation":[{"name":"Shizuoka University, Shizuoka, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Minoru","family":"Watanabe","sequence":"additional","affiliation":[{"name":"Shizuoka University, Shizuoka, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,3,25]]},"reference":[{"key":"e_1_2_1_1_1","first-page":"356","volume-title":"International Conference on Anti-counterfeiting, Seurity and Identification","author":"Pizhou Y.","year":"2008"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.239"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/45.464688"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCN.1991.208101"},{"key":"e_1_2_1_5_1","first-page":"66","article-title":"Mono-instruction computer on a dynamically reconfigurable gatearray","author":"Nihira Y.","year":"2012","journal-title":"Workshop on Synthesis And System Integration of Mixed Information technologies"},{"key":"e_1_2_1_6_1","unstructured":"Altera Corporation \"Altera Devies \" http:\/\/www.altera.com.  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Watanabe F. Kobayashi \"A logic synthesis and place and route environment for ORGAs \" International conferene on engineering of reconfigurable systems and algorithms pp. 237--238 2006.  M. Watanabe F. Kobayashi \"A logic synthesis and place and route environment for ORGAs \" International conferene on engineering of reconfigurable systems and algorithms pp. 237--238 2006."}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2460216.2460231","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2460216.2460231","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:18:46Z","timestamp":1750234726000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2460216.2460231"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,3,25]]},"references-count":19,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2012,12,25]]}},"alternative-id":["10.1145\/2460216.2460231"],"URL":"https:\/\/doi.org\/10.1145\/2460216.2460231","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2012,3,25]]},"assertion":[{"value":"2012-03-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}