{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,22]],"date-time":"2026-01-22T06:06:54Z","timestamp":1769062014481,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2013,5,29]],"date-time":"2013-05-29T00:00:00Z","timestamp":1369785600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2013,5,29]]},"DOI":"10.1145\/2463209.2488845","type":"proceedings-article","created":{"date-parts":[[2013,5,28]],"date-time":"2013-05-28T16:35:41Z","timestamp":1369758941000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":23,"title":["An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem"],"prefix":"10.1145","author":[{"given":"Juyeon","family":"Kim","sequence":"first","affiliation":[{"name":"Seoul National University, Seoul, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Deokjin","family":"Joo","sequence":"additional","affiliation":[{"name":"Seoul National University, Seoul, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Taewhan","family":"Kim","sequence":"additional","affiliation":[{"name":"Seoul National University, Seoul, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,5,29]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309983"},{"key":"e_1_3_2_1_2_1","unstructured":"J. Cong C. Koh and K. Leung \"Simultaneous buffer and wire sizing for performance and power optimization \" in ISLPED 1996.   J. Cong C. Koh and K. Leung \"Simultaneous buffer and wire sizing for performance and power optimization \" in ISLPED 1996."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.784121"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/332357.332370"},{"key":"e_1_3_2_1_5_1","unstructured":"T. Okamoto and J. Cong \"Buffered steiner tree construction with wire sizing for interconnect layout optimization \" in ICCAD 1996.   T. Okamoto and J. Cong \"Buffered steiner tree construction with wire sizing for interconnect layout optimization \" in ICCAD 1996."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825875"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.846362"},{"key":"e_1_3_2_1_8_1","unstructured":"S. Hu and J. Hu \"Unified adaptivity optimization of clock and logic signals \" in ICCAD 2007.   S. Hu and J. Hu \"Unified adaptivity optimization of clock and logic signals \" in ICCAD 2007."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1231996.1232002"},{"key":"e_1_3_2_1_10_1","unstructured":"J.-L. Tsai and L. Zhang \"Statistical timing analysis driven post-silicon-tunable clock-tree synthesis \" in ICCAD 2005.   J.-L. Tsai and L. Zhang \"Statistical timing analysis driven post-silicon-tunable clock-tree synthesis \" in ICCAD 2005."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"crossref","unstructured":"E. Takahashi Y. Kasai M. Murakawa and T. Higuchi \"A post-silicon clock timing adjustment using genetic algorithms \" in Symposium on VLSI Circuits 2003.  E. Takahashi Y. Kasai M. Murakawa and T. Higuchi \"A post-silicon clock timing adjustment using genetic algorithms \" in Symposium on VLSI Circuits 2003.","DOI":"10.1109\/JSSC.2004.824706"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"S. Tam S. Rusu U. Nagarji Desai R. Kim J. Zhang and I. Young \"Clock generation and distribution for the first IA-64 microprocessor \" IEEE JSSC 2000.  S. Tam S. Rusu U. Nagarji Desai R. Kim J. Zhang and I. Young \"Clock generation and distribution for the first IA-64 microprocessor \" IEEE JSSC 2000.","DOI":"10.1109\/4.881198"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687500"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2061654"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"K.-Y. Lin H.-T. Lin and T.-Y. Ho \"An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs \" in ASPDAC 2011.   K.-Y. Lin H.-T. Lin and T.-Y. Ho \"An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs \" in ASPDAC 2011.","DOI":"10.1109\/ASPDAC.2011.5722304"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"crossref","unstructured":"K.-H. Lim and T. Kim \"An optimal algorithm for allocation placement and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs \" in ASPDAC 2011.   K.-H. Lim and T. Kim \"An optimal algorithm for allocation placement and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs \" in ASPDAC 2011.","DOI":"10.1109\/ASPDAC.2011.5722242"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382651"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2003695.2003708"}],"event":{"name":"DAC '13: The 50th Annual Design Automation Conference 2013","location":"Austin Texas","acronym":"DAC '13","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 50th Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2463209.2488845","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2463209.2488845","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:39:29Z","timestamp":1750235969000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2463209.2488845"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,5,29]]},"references-count":18,"alternative-id":["10.1145\/2463209.2488845","10.1145\/2463209"],"URL":"https:\/\/doi.org\/10.1145\/2463209.2488845","relation":{},"subject":[],"published":{"date-parts":[[2013,5,29]]},"assertion":[{"value":"2013-05-29","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}