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Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2013,5]]},"abstract":"<jats:p>It has been predicted that a processor's caches could occupy as much as 90% of chip area a few technology nodes from the current ones. In this article, we investigate the use of multilevel spin-transfer torque RAM (STT-RAM) cells in the design of processor caches. We start with examining the access (read and write) scheme for multilevel cell (MLC) STT-RAM from a circuit design perspective, detailing the read and write circuits. Compared to traditional SRAM caches, a multilevel cell (MLC) STT-RAM cache design is denser, fast, and requires less energy. However, a number of critical architecture-level issues remain to be solved before MLC STT-RAM technology can be deployed in processor caches. We shall offer solutions to the issue of bit encoding as well as tackle the write endurance problem. In particular, the latter has been neglected in previous works on STT-RAM caches. We propose a set remapping scheme that can potentially prolong the lifetime of a MLC STT-RAM cache by 80\u00d7 on average. Furthermore, a method for recovering the performance that may be lost in some applications due to set remapping is proposed. The impacts of process variations of the MLC STT-RAM cell on the robustness of the memory hierarchy is also discussed, together with various enhancement techniques, namely, ECC and design redundancy.<\/jats:p>","DOI":"10.1145\/2463585.2463592","type":"journal-article","created":{"date-parts":[[2013,6,5]],"date-time":"2013-06-05T12:09:34Z","timestamp":1370434174000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":44,"title":["On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations"],"prefix":"10.1145","volume":"9","author":[{"given":"Yiran","family":"Chen","sequence":"first","affiliation":[{"name":"University of Pittsburgh"}]},{"given":"Weng-Fai","family":"Wong","sequence":"additional","affiliation":[{"name":"National University of Singapore"}]},{"given":"Hai","family":"Li","sequence":"additional","affiliation":[{"name":"Polytechnic Institute of New York University"}]},{"given":"Cheng-Kok","family":"Koh","sequence":"additional","affiliation":[{"name":"Purdue University"}]},{"given":"Yaojun","family":"Zhang","sequence":"additional","affiliation":[{"name":"University of Pittsburgh"}]},{"given":"Wujie","family":"Wen","sequence":"additional","affiliation":[{"name":"University of Pittsburgh"}]}],"member":"320","published-online":{"date-parts":[[2013,5,29]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609462"},{"volume-title":"Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing. 21--26","author":"Calligaro C.","key":"e_1_2_1_2_1","unstructured":"Calligaro , C. , Daniele , V. , Gastaldi , R. , Manstretta , A. , and Torelli , G . 1995. A new serial sensing approach for multistorage non-volatile memories . In Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing. 21--26 . Calligaro, C., Daniele, V., Gastaldi, R., Manstretta, A., and Torelli, G. 1995. A new serial sensing approach for multistorage non-volatile memories. In Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing. 21--26."},{"volume-title":"Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing. 96--101","author":"Calligaro C.","key":"e_1_2_1_3_1","unstructured":"Calligaro , C. , Gastaldi , R. , Manstretta , A. , and Torelli , G . 1997. A high-speed parallel sensing scheme for multi-level non-volatile memories . In Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing. 96--101 . Calligaro, C., Gastaldi, R., Manstretta, A., and Torelli, G. 1997. A high-speed parallel sensing scheme for multi-level non-volatile memories. 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