{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T16:32:08Z","timestamp":1774801928054,"version":"3.50.1"},"reference-count":22,"publisher":"Association for Computing Machinery (ACM)","issue":"2s","license":[{"start":{"date-parts":[[2013,5,1]],"date-time":"2013-05-01T00:00:00Z","timestamp":1367366400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100013453","name":"GSRC","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100013453","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"name":"GRC"},{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100006227","name":"Lawrence Livermore National Laboratory, Office of Science","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006227","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2013,5]]},"abstract":"<jats:p>Escalating variations in modern CMOS designs have become a threat to Moore\u2019s law. In light of the increasing costs of standard worst-case design practices, timing speculation has become a popular approach for dealing with static and dynamic non-determinism and increasing yield. Timing speculative architectures allow conservative guardbands to be relaxed, increasing efficiency at the expense of occasional errors, which are corrected or tolerated by an error resilience mechanism. Previous work has proposed circuit- or design-level optimizations that manipulate the error rate behavior of a design to increase the efficiency of timing speculation. In this article, we investigate whether architectural optimizations can also manipulate error rate behavior to significantly increase the effectiveness of timing speculation. To this end, we demonstrate how error rate behavior indeed depends on processor architecture and that architectural optimizations can be used to manipulate the error rate behavior of a processor. Using timing speculation-aware architectural optimizations, we demonstrate enhanced overscaling and up to 29% additional energy savings for processors that employ Razor-based timing speculation.<\/jats:p>","DOI":"10.1145\/2465787.2465791","type":"journal-article","created":{"date-parts":[[2013,6,5]],"date-time":"2013-06-05T12:09:34Z","timestamp":1370434174000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Exploiting Timing Error Resilience in Processor Architecture"],"prefix":"10.1145","volume":"12","author":[{"given":"John","family":"Sartori","sequence":"first","affiliation":[{"name":"University of Illinois at Urbana-Champaign"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rakesh","family":"Kumar","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,5]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629915"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000067"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566437"},{"key":"e_1_2_1_5_1","volume-title":"T., Flautner, K.","author":"Ernst D.","year":"2003","unstructured":"Ernst , D. , Kim , N. S. , Das , S. , Pant , S. , Rao , R. , Pham , T. , Ziesler , C. , Blaauw , D. , Austin , T., Flautner, K. , and Mudge, T. 2003 . Razor : A low-power pipeline based on circuit-level timing speculation. In Proceedings of MICRO. 7. Ernst, D., Kim, N. S., Das, S., Pant, S., Rao, R., Pham, T., Ziesler, C., Blaauw, D., Austin, T., Flautner, K., and Mudge, T. 2003. Razor: A low-power pipeline based on circuit-level timing speculation. In Proceedings of MICRO. 7."},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of ISSCC.","author":"Fujimura Y.","unstructured":"Fujimura , Y. , Hirabayashi , O. , Sasaki , T. , Suzuki , A. , Kawasumi , A. , Takeyama , Y. , Kushida , K. , Fukano , G. , Katayama , A. , Niki , Y. , and Yabe , T . 2010. A configurable sram with constant-negative-level write buffer for low voltage operation with 0.149&mu;m2 cell in 32nm high-k\/metal gate cmos . In Proceedings of ISSCC. Fujimura, Y., Hirabayashi, O., Sasaki, T., Suzuki, A., Kawasumi, A., Takeyama, Y., Kushida, K., Fukano, G., Katayama, A., Niki, Y., and Yabe, T. 2010. A configurable sram with constant-negative-level write buffer for low voltage operation with 0.149&mu;m2 cell in 32nm high-k\/metal gate cmos. In Proceedings of ISSCC."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/1299042.1299049"},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of HPCA.","author":"Greskamp B.","unstructured":"Greskamp , B. , Wan , L. , Karpuzcu , W. , Cook , J. , Torrellas , J. , Chen , D. , and Zilles , C . 2009. Blueshift: Designing processors for timing speculation from the ground up . In Proceedings of HPCA. Greskamp, B., Wan, L., Karpuzcu, W., Cook, J., Torrellas, J., Chen, D., and Zilles, C. 2009. Blueshift: Designing processors for timing speculation from the ground up. In Proceedings of HPCA."},{"key":"e_1_2_1_9_1","volume-title":"Proceedings of JILP.","author":"Hamerly G.","unstructured":"Hamerly , G. , Perelman , E. , Lau , J. , and Calder , B . 2005. Simpoint 3.0: Faster and more flexible program analysis . In Proceedings of JILP. Hamerly, G., Perelman, E., Lau, J., and Calder, B. 2005. Simpoint 3.0: Faster and more flexible program analysis. In Proceedings of JILP."},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of MICRO. 117","author":"Hartstein A.","unstructured":"Hartstein , A. and Puzak , T . 2003. Optimum power\/performance pipeline depth . In Proceedings of MICRO. 117 . Hartstein, A. and Puzak, T. 2003. Optimum power\/performance pipeline depth. In Proceedings of MICRO. 117."},{"key":"e_1_2_1_11_1","volume-title":"Intel Atom Processor Z5xx Series","author":"Intel Corporation 2008.","unstructured":"Intel Corporation 2008. Intel Atom Processor Z5xx Series . Intel Corporation . http:\/\/www.intel.com\/. Intel Corporation 2008. Intel Atom Processor Z5xx Series. Intel Corporation. http:\/\/www.intel.com\/."},{"key":"e_1_2_1_12_1","volume-title":"Proceedings of HPCA.","author":"Kahng A.","unstructured":"Kahng , A. , Kang , S. , Kumar , R. , and Sartori , J . 2010a. Designing processors from the ground up to allow voltage\/reliability tradeoffs . In Proceedings of HPCA. Kahng, A., Kang, S., Kumar, R., and Sartori, J. 2010a. Designing processors from the ground up to allow voltage\/reliability tradeoffs. In Proceedings of HPCA."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837481"},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of ASPDAC.","author":"Kahng A.","unstructured":"Kahng , A. , Kang , S. , Kumar , R. , and Sartori , J . 2010c. Slack redistribution for graceful degradation under voltage overscaling . In Proceedings of ASPDAC. Kahng, A., Kang, S., Kumar, R., and Sartori, J. 2010c. Slack redistribution for graceful degradation under voltage overscaling. In Proceedings of ASPDAC."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1993.393383"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233587"},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of DATE.","author":"Narayanan S.","unstructured":"Narayanan , S. , Sartori , J. , Kumar , R. , and Jones , D . 2010. Scalable stochastic processors . In Proceedings of DATE. Narayanan, S., Sartori, J., Kumar, R., and Jones, D. 2010. Scalable stochastic processors. In Proceedings of DATE."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264201"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629929"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771810"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785533"},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the 22nd Annual Computer Measurement Group Conference.","author":"Tullsen D. M.","year":"1996","unstructured":"Tullsen , D. M. 1996 . Simulation and modeling of a simultaneous multithreading processor . In Proceedings of the 22nd Annual Computer Measurement Group Conference. Tullsen, D. M. 1996. Simulation and modeling of a simultaneous multithreading processor. In Proceedings of the 22nd Annual Computer Measurement Group Conference."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2465787.2465791","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2465787.2465791","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:39:16Z","timestamp":1750235956000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2465787.2465791"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,5]]},"references-count":22,"journal-issue":{"issue":"2s","published-print":{"date-parts":[[2013,5]]}},"alternative-id":["10.1145\/2465787.2465791"],"URL":"https:\/\/doi.org\/10.1145\/2465787.2465791","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,5]]},"assertion":[{"value":"2011-06-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-08-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-05-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}