{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:22:12Z","timestamp":1750306932815,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2013,3,18]],"date-time":"2013-03-18T00:00:00Z","timestamp":1363564800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2013,3,18]]},"DOI":"10.1145\/2480362.2480661","type":"proceedings-article","created":{"date-parts":[[2013,5,1]],"date-time":"2013-05-01T19:47:45Z","timestamp":1367437665000},"page":"1595-1602","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Analyzing resource interdependencies in multi-core architectures to improve scheduling decisions"],"prefix":"10.1145","author":[{"given":"Anselm","family":"Busse","sequence":"first","affiliation":[{"name":"Technische Universit\u00e4t Berlin, Berlin, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jan H.","family":"Sch\u00f6nherr","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Berlin, Berlin, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthias","family":"Diener","sequence":"additional","affiliation":[{"name":"Federal University of Rio, Grande do Sul, Porto Alegre, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gero","family":"M\u00fchl","sequence":"additional","affiliation":[{"name":"University of Rostock, Rostock, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jan","family":"Richling","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Berlin, Berlin, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,3,18]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Jan.","author":"Devices Advanced Micro","year":"2012","unstructured":"Advanced Micro Devices . Software Optimization Guide for AMD Family 15h Processors , Jan. 2012 . Advanced Micro Devices. Software Optimization Guide for AMD Family 15h Processors, Jan. 2012."},{"key":"e_1_3_2_1_3_1","first-page":"399","volume-title":"Proceedings of the USENIX 2005 Annual Technical Conference (ATEC '05)","author":"Bulpin J. R.","year":"2005","unstructured":"J. R. Bulpin and I. A. Pratt . Hyper-threading aware process scheduling heuristics . In Proceedings of the USENIX 2005 Annual Technical Conference (ATEC '05) , pages 399 -- 402 , Berkeley, CA, USA , 2005 . USENIX Association. J. R. Bulpin and I. A. Pratt. Hyper-threading aware process scheduling heuristics. In Proceedings of the USENIX 2005 Annual Technical Conference (ATEC '05), pages 399--402, Berkeley, CA, USA, 2005. USENIX Association."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2010.5470399"},{"key":"e_1_3_2_1_6_1","volume-title":"White Paper","author":"Intel Corporation","year":"2011","unstructured":"Intel Corporation . Utilizing intel AVX with cakewalk SONAR* X1 . White Paper , 2011 . Intel Corporation. Utilizing intel AVX with cakewalk SONAR* X1. White Paper, 2011."},{"key":"e_1_3_2_1_7_1","volume-title":"Apr.","author":"Intel Corporation","year":"2012","unstructured":"Intel Corporation . Intel 64 and IA-32 Architectures Optimization Reference Manual , Apr. 2012 . Intel Corporation. Intel 64 and IA-32 Architectures Optimization Reference Manual, Apr. 2012."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151003"},{"key":"e_1_3_2_1_11_1","first-page":"279","volume-title":"Proceedings of the USENIX 1996 Annual Technical Conference (ATEC '96)","author":"McVoy L.","year":"1996","unstructured":"L. McVoy and C. Staelin . lmbench: portable tools for performance analysis . In Proceedings of the USENIX 1996 Annual Technical Conference (ATEC '96) , pages 279 -- 294 , Berkeley, CA, USA , 1996 . USENIX Association. L. McVoy and C. Staelin. lmbench: portable tools for performance analysis. In Proceedings of the USENIX 1996 Annual Technical Conference (ATEC '96), pages 279--294, Berkeley, CA, USA, 1996. USENIX Association."},{"key":"e_1_3_2_1_12_1","volume-title":"Proceedings of the Workshop on Power Aware Computing and Systems (HotPower '08)","author":"Merkel A.","year":"2008","unstructured":"A. Merkel and F. Bellosa . Memory-aware scheduling for energy efficiency on multicore processors . In Proceedings of the Workshop on Power Aware Computing and Systems (HotPower '08) , Berkeley, CA, USA , Dec. 2008 . USENIX Association. A. Merkel and F. Bellosa. Memory-aware scheduling for energy efficiency on multicore processors. In Proceedings of the Workshop on Power Aware Computing and Systems (HotPower '08), Berkeley, CA, USA, Dec. 2008. USENIX Association."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1352592.1352594"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2010.08.020"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-31202-1_7"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2010.36"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1791314.1791323"},{"key":"e_1_3_2_1_18_1","first-page":"367","volume-title":"Workshop Proceedings of the 23rd International Conference on Architecture of Computing Systems (ARCS '10)","author":"Sch\u00f6nherr J. H.","year":"2010","unstructured":"J. H. Sch\u00f6nherr , J. Richling , M. Werner , and G. M\u00fchl . A scheduling approach for efficient utilization of hardware-driven frequency scaling . In Workshop Proceedings of the 23rd International Conference on Architecture of Computing Systems (ARCS '10) , pages 367 -- 376 , Berlin, Germany , Feb. 2010 . VDE Verlag. J. H. Sch\u00f6nherr, J. Richling, M. Werner, and G. M\u00fchl. A scheduling approach for efficient utilization of hardware-driven frequency scaling. In Workshop Proceedings of the 23rd International Conference on Architecture of Computing Systems (ARCS '10), pages 367--376, Berlin, Germany, Feb. 2010. VDE Verlag."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1531793.1531804"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1945023.1945032"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736036"}],"event":{"name":"SAC '13: SAC '13","sponsor":["SIGAPP ACM Special Interest Group on Applied Computing"],"location":"Coimbra Portugal","acronym":"SAC '13"},"container-title":["Proceedings of the 28th Annual ACM Symposium on Applied Computing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2480362.2480661","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2480362.2480661","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:35:39Z","timestamp":1750235739000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2480362.2480661"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3,18]]},"references-count":17,"alternative-id":["10.1145\/2480362.2480661","10.1145\/2480362"],"URL":"https:\/\/doi.org\/10.1145\/2480362.2480661","relation":{},"subject":[],"published":{"date-parts":[[2013,3,18]]},"assertion":[{"value":"2013-03-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}