{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:05:03Z","timestamp":1761581103945,"version":"3.41.0"},"reference-count":130,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2013,6,1]],"date-time":"2013-06-01T00:00:00Z","timestamp":1370044800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Comput. Surv."],"published-print":{"date-parts":[[2013,6]]},"abstract":"<jats:p>\n            This article reviews four popular mathematical formalisms\u2014\n            <jats:italic>queueing theory, network calculus, schedulability analysis<\/jats:italic>\n            , and\n            <jats:italic>dataflow analysis<\/jats:italic>\n            \u2014and how they have been applied to the analysis of on-chip communication performance in Systems-on-Chip. The article discusses the basic concepts and results of each formalism and provides examples of how they have been used in Networks-on-Chip (NoCs) performance analysis. Also, the respective strengths and weaknesses of each technique and its suitability for a specific purpose are investigated. An open research issue is a unified analytical model for a comprehensive performance evaluation of NoCs. To this end, this article reviews the attempts that have been made to bridge these formalisms.\n          <\/jats:p>","DOI":"10.1145\/2480741.2480755","type":"journal-article","created":{"date-parts":[[2013,7,1]],"date-time":"2013-07-01T12:27:28Z","timestamp":1372681648000},"page":"1-41","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":32,"title":["Mathematical formalisms for performance evaluation of networks-on-chip"],"prefix":"10.1145","volume":"45","author":[{"given":"Abbas Eslami","family":"Kiasari","sequence":"first","affiliation":[{"name":"KTH Royal Institute of Technology"}]},{"given":"Axel","family":"Jantsch","sequence":"additional","affiliation":[{"name":"KTH Royal Institute of Technology"}]},{"given":"Zhonghai","family":"Lu","sequence":"additional","affiliation":[{"name":"KTH Royal Institute of Technology"}]}],"member":"320","published-online":{"date-parts":[[2013,7,3]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.1261839"},{"volume-title":"Proceedings of the 7th International Conference on Real-Time Systems and Applications (RTCSA'00)","author":"Andersson B.","key":"e_1_2_1_2_1","unstructured":"Andersson , B. and Jonsson , J . 2000. Fixed-priority preemptive multiprocessor scheduling: To partition or not to partition . In Proceedings of the 7th International Conference on Real-Time Systems and Applications (RTCSA'00) . IEEE Computer Society, 337--346. Andersson, B. and Jonsson, J. 2000. Fixed-priority preemptive multiprocessor scheduling: To partition or not to partition. In Proceedings of the 7th International Conference on Real-Time Systems and Applications (RTCSA'00). IEEE Computer Society, 337--346."},{"volume-title":"Proceedings of the 22nd IEEE Real-Time Systems Symposium (RTSS'01)","author":"Andersson B.","key":"e_1_2_1_3_1","unstructured":"Andersson , B. , Baruah , S. , and Jonsson , J . 2001. Static-priority scheduling on multiprocessors . In Proceedings of the 22nd IEEE Real-Time Systems Symposium (RTSS'01) . IEEE Computer Society, 193--202. Andersson, B., Baruah, S., and Jonsson, J. 2001. Static-priority scheduling on multiprocessors. In Proceedings of the 22nd IEEE Real-Time Systems Symposium (RTSS'01). IEEE Computer Society, 193--202."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1049\/sej.1993.0034"},{"volume-title":"Proceedings of the 8th Workshop on Quantitative Aspects of Programming Languages (QAPL'10)","author":"Altisen K.","key":"e_1_2_1_5_1","unstructured":"Altisen , K. , Liu , Y. , and Moy , M . 2010. Performance evaluation of components using a granularity-based interface between real-time calculus and timed automata . In Proceedings of the 8th Workshop on Quantitative Aspects of Programming Languages (QAPL'10) . 16--23. Altisen, K., Liu, Y., and Moy, M. 2010. Performance evaluation of components using a granularity-based interface between real-time calculus and timed automata. In Proceedings of the 8th Workshop on Quantitative Aspects of Programming Languages (QAPL'10). 16--23."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/956418.956614"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.simpat.2010.10.008"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.707545"},{"key":"e_1_2_1_9_1","doi-asserted-by":"crossref","unstructured":"Bekooij M. J. G. Moriera O. Poplavko P. Mesman B. Pastrnak M. and \n      Meerbergen J\n  . \n  2004\n  . Predictable embedded multiprocessor system design. In Proceedings of the International Workshop on Software and Compilers for Embedded Systems Lecture Notes in Computer Science vol. \n  3199 Springer 77--91.  Bekooij M. J. G. Moriera O. Poplavko P. Mesman B. Pastrnak M. and Meerbergen J. 2004. Predictable embedded multiprocessor system design. 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