{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:22:35Z","timestamp":1750306955531,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":14,"publisher":"ACM","license":[{"start":{"date-parts":[[2013,5,2]],"date-time":"2013-05-02T00:00:00Z","timestamp":1367452800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2013,5,2]]},"DOI":"10.1145\/2483028.2483065","type":"proceedings-article","created":{"date-parts":[[2013,5,7]],"date-time":"2013-05-07T20:51:54Z","timestamp":1367959914000},"page":"77-82","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A portable high-frequency digitally controlled oscillator (DCO)"],"prefix":"10.1145","author":[{"given":"Muhammad E.S.","family":"Elrabaa","sequence":"first","affiliation":[{"name":"King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,5,2]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/82.775392"},{"key":"e_1_3_2_1_2_1","first-page":"80","volume-title":"A digitally controlled oscillator constructed using adjustable resistors,\" in Proceedings of IEEE Southwest Symposium on Mixed-Signal Design","author":"Saint-Laurent M.","year":"2001","unstructured":"M. Saint-Laurent and G. P. Muyshondt , \" A digitally controlled oscillator constructed using adjustable resistors,\" in Proceedings of IEEE Southwest Symposium on Mixed-Signal Design , pp. 80 -- 82 , 2001 . M. Saint-Laurent and G. P. Muyshondt, \"A digitally controlled oscillator constructed using adjustable resistors,\" in Proceedings of IEEE Southwest Symposium on Mixed-Signal Design, pp. 80--82, 2001."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2004.842067"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","unstructured":"P. Raha S. Randall R. Jennings B. Helmick A. Amerasekera and B. Haroun \"A robust digital delay line architecture in a 0.13\u03bcm CMOS technology node for reduced design and process sensitivities \" in Proceedings of the International Symposium on Quality Electronic Design (ISQED '02) pp. 148--153 2002. P. Raha S. Randall R. Jennings B. Helmick A. Amerasekera and B. Haroun \"A robust digital delay line architecture in a 0.13\u03bcm CMOS technology node for reduced design and process sensitivities \" in Proceedings of the International Symposium on Quality Electronic Design (ISQED '02) pp. 148--153 2002.","DOI":"10.1109\/ISQED.2002.996719"},{"key":"e_1_3_2_1_5_1","first-page":"352","article-title":"Delay Circuit Having a Capacitor and Having Reduced Power Supply Voltage Dependency","volume":"7","author":"Tomita Hiroyoshi","year":"2008","unstructured":"Hiroyoshi Tomita , \" Delay Circuit Having a Capacitor and Having Reduced Power Supply Voltage Dependency ,\" US Patent 7 , 352 ,223 B2, April 1, 2008 . Hiroyoshi Tomita, \"Delay Circuit Having a Capacitor and Having Reduced Power Supply Voltage Dependency,\" US Patent 7,352,223 B2, April 1, 2008.","journal-title":"US Patent"},{"key":"e_1_3_2_1_6_1","first-page":"5449","volume-title":"Proceedings of ISCAS","volume":"6","author":"Wu Chia-Tsun","year":"2005","unstructured":"Chia-Tsun Wu , Wei Wang , I- Chyn Wey , and An-Yeu (Andy) Wu , \" A Scalable DCO Design for Portable ADPLL Designs ,\" in Proceedings of ISCAS 2005 , pp. 5449 -- 5452 , Vol. 6 . Chia-Tsun Wu, Wei Wang, I-Chyn Wey, and An-Yeu (Andy) Wu, \"A Scalable DCO Design for Portable ADPLL Designs,\" in Proceedings of ISCAS 2005, pp. 5449 -- 5452, Vol. 6."},{"key":"e_1_3_2_1_7_1","first-page":"1","volume-title":"Proceedings Int. Sym. on VLSI Design, Automation and Test","author":"Sheng Duo","year":"2006","unstructured":"Duo Sheng , Ching-Che Chung , and Chen-Yi Lee , \" An All-Digital Phase-Locked Loop with High-Resolution for SoC Applications ,\" in Proceedings Int. Sym. on VLSI Design, Automation and Test , pp. 1 -- 4 , 2006 . Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, \"An All-Digital Phase-Locked Loop with High-Resolution for SoC Applications,\" in Proceedings Int. Sym. on VLSI Design, Automation and Test, pp. 1--4, 2006."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.903782"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2087991"},{"key":"e_1_3_2_1_10_1","first-page":"366","article-title":"Digital Delay Line","volume":"6","author":"Ishimi Kouichi","year":"2002","unstructured":"Kouichi Ishimi , \" Digital Delay Line ,\" US Patent 6 , 366 ,150 B1, April 2, 2002 . Kouichi Ishimi, \"Digital Delay Line,\" US Patent 6,366,150 B1, April 2, 2002.","journal-title":"US Patent"},{"key":"e_1_3_2_1_11_1","first-page":"952","article-title":"Programmable Digital Delay","volume":"7","author":"Warren Robert G.","year":"2011","unstructured":"Robert G. Warren , \" Programmable Digital Delay ,\" US Patent 7 , 952 ,411 B2, May 31, 2011 . Robert G. Warren, \"Programmable Digital Delay,\" US Patent 7,952,411 B2, May 31, 2011.","journal-title":"US Patent"},{"key":"e_1_3_2_1_12_1","first-page":"1268","volume-title":"Proceedings of 14th IEEE Int. Conf. on Digital Electronics, Circuits and Systems (ICECS'07)","author":"Huang Hong-Yi","year":"2007","unstructured":"Hong-Yi Huang , Jen-Chieh Liu , and Kuo-Hsing Cheng , \" All-Digital PLL Using Pulse-Based DCO,\" in Proceedings of 14th IEEE Int. Conf. on Digital Electronics, Circuits and Systems (ICECS'07) , pp. 1268 -- 1271 , 2007 . Hong-Yi Huang, Jen-Chieh Liu, and Kuo-Hsing Cheng, \"All-Digital PLL Using Pulse-Based DCO,\" in Proceedings of 14th IEEE Int. Conf. on Digital Electronics, Circuits and Systems (ICECS'07), pp. 1268--1271, 2007."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2082272"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2010.2095426"}],"event":{"name":"GLSVLSI'13: Great Lakes Symposium on VLSI 2013","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Paris France","acronym":"GLSVLSI'13"},"container-title":["Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2483028.2483065","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2483028.2483065","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:39:06Z","timestamp":1750235946000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2483028.2483065"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,5,2]]},"references-count":14,"alternative-id":["10.1145\/2483028.2483065","10.1145\/2483028"],"URL":"https:\/\/doi.org\/10.1145\/2483028.2483065","relation":{},"subject":[],"published":{"date-parts":[[2013,5,2]]},"assertion":[{"value":"2013-05-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}