{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:22:36Z","timestamp":1750306956321,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":13,"publisher":"ACM","license":[{"start":{"date-parts":[[2013,5,2]],"date-time":"2013-05-02T00:00:00Z","timestamp":1367452800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2013,5,2]]},"DOI":"10.1145\/2483028.2483086","type":"proceedings-article","created":{"date-parts":[[2013,5,7]],"date-time":"2013-05-07T20:51:54Z","timestamp":1367959914000},"page":"173-178","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Scaling RTL property checking using feasible path analysisand decomposition"],"prefix":"10.1145","author":[{"given":"Lingyi","family":"Liu","sequence":"first","affiliation":[{"name":"University of Illinois at Urbana Champaign, Urbana, IL, USA"}]},{"given":"Shobha","family":"Vasudevan","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana Champaign, Urbana, IL, USA"}]}],"member":"320","published-online":{"date-parts":[[2013,5,2]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"\"Yices SMT solver http:\/\/yices.csl.sri.com\/.\"  \"Yices SMT solver http:\/\/yices.csl.sri.com\/.\""},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10009-008-0091-0"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391507"},{"key":"e_1_3_2_1_4_1","volume-title":"dissertation","author":"Vasudevan S.","year":"2007","unstructured":"S. Vasudevan , \"High level static analysis of system descriptions for taming verification complexity,\" Ph. D. dissertation , The University of Texas at Austin, 2007 . S. Vasudevan, \"High level static analysis of system descriptions for taming verification complexity,\" Ph.D. dissertation, The University of Texas at Austin, 2007."},{"key":"e_1_3_2_1_5_1","first-page":"298","article-title":"Program slicing of hardware description languages","author":"Clarke E. M.","year":"1999","unstructured":"E. M. Clarke , M. Fujita , S. P. Rajan , T. W. Reps , S. Shankar , and T. Teitelbaum , \" Program slicing of hardware description languages ,\" in Proc. of CHARME , 1999 , pp. 298 -- 312 . E. M. Clarke, M. Fujita, S. P. Rajan, T. W. Reps, S. Shankar, and T. Teitelbaum, \"Program slicing of hardware description languages,\" in Proc. of CHARME, 1999, pp. 298--312.","journal-title":"Proc. of CHARME"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1022885523034"},{"key":"e_1_3_2_1_7_1","unstructured":"\"Openrisc web page: http:\/\/www.opencores.org.\"  \"Openrisc web page: http:\/\/www.opencores.org.\""},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1011276507260"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-6423(99)00030-1"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065036"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1081706.1081750"},{"key":"e_1_3_2_1_12_1","first-page":"1596","article-title":"Efficient validation input generation in RTL by hybridized source code analysis","author":"Liu L.","year":"2011","unstructured":"L. Liu and S. Vasudevan , \" Efficient validation input generation in RTL by hybridized source code analysis ,\" in Proc. of DATE , 2011 , pp. 1596 -- 1601 . L. Liu and S. Vasudevan, \"Efficient validation input generation in RTL by hybridized source code analysis,\" in Proc. of DATE, 2011, pp. 1596--1601.","journal-title":"Proc. of DATE"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233664"}],"event":{"name":"GLSVLSI'13: Great Lakes Symposium on VLSI 2013","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Paris France","acronym":"GLSVLSI'13"},"container-title":["Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2483028.2483086","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2483028.2483086","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:39:06Z","timestamp":1750235946000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2483028.2483086"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,5,2]]},"references-count":13,"alternative-id":["10.1145\/2483028.2483086","10.1145\/2483028"],"URL":"https:\/\/doi.org\/10.1145\/2483028.2483086","relation":{},"subject":[],"published":{"date-parts":[[2013,5,2]]},"assertion":[{"value":"2013-05-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}