{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:22:36Z","timestamp":1750306956415,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2013,5,2]],"date-time":"2013-05-02T00:00:00Z","timestamp":1367452800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2013,5,2]]},"DOI":"10.1145\/2483028.2483097","type":"proceedings-article","created":{"date-parts":[[2013,5,7]],"date-time":"2013-05-07T20:51:54Z","timestamp":1367959914000},"page":"221-226","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Performance\/reliability trade-off in superscalar processors for aggressive NBTI restoration of functional units"],"prefix":"10.1145","author":[{"given":"Simone","family":"Corbetta","sequence":"first","affiliation":[{"name":"Politecnico di Milano, Milano, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"William","family":"Fornaciari","sequence":"additional","affiliation":[{"name":"Politecnico di Milano, Milano, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,5,2]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPFA.2007.4378050"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2004.03.019"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320885"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763151"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICASIC.2007.4415882"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000067"},{"volume-title":"Present and Future. In Proceedings of the 10th International Workshop on Worst-Case Execution Time Analysis","year":"2010","author":"Gustafsson J.","key":"e_1_3_2_1_7_1"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/1128020.1128563"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013249"},{"key":"e_1_3_2_1_10_1","first-page":"132","volume-title":"SAMOS 2008. International Conference on","author":"Kejariwal A.","year":"2008"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1229175.1229176"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_3_2_1_13_1","unstructured":"MASTAR - Model for Assessment of CMOS Technology and Roadmaps http:\/\/www.itrs.net\/models.html.  MASTAR - Model for Assessment of CMOS Technology and Roadmaps http:\/\/www.itrs.net\/models.html."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751891"},{"issue":"1","key":"e_1_3_2_1_15_1","first-page":"36","article-title":"Performance characterization of spec cpu 2006 benchmarks on intel core 2 duo processor. Computers and Software Engineering","volume":"2","author":"Prakash T. K.","year":"2008","journal-title":"ISTAT Transactions on"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.2008.43"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006238"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1835420.1835421"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810400"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.5555\/1899721.1899829"},{"key":"e_1_3_2_1_21_1","unstructured":"The modified SPLASH-2 benchmark suite http:\/\/www.capsl.udel.edu\/splash\/.  The modified SPLASH-2 benchmark suite http:\/\/www.capsl.udel.edu\/splash\/."},{"issue":"4","key":"e_1_3_2_1_22_1","first-page":"509","article-title":"Compact modeling and simulation of circuit Reliability for 65-nm cmos technology. Device and Materials Reliability","volume":"7","author":"Wang W.","year":"2007","journal-title":"IEEE Transactions on"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278573"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810264"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/1950815.1950936"}],"event":{"name":"GLSVLSI'13: Great Lakes Symposium on VLSI 2013","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Paris France","acronym":"GLSVLSI'13"},"container-title":["Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2483028.2483097","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2483028.2483097","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:39:06Z","timestamp":1750235946000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2483028.2483097"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,5,2]]},"references-count":25,"alternative-id":["10.1145\/2483028.2483097","10.1145\/2483028"],"URL":"https:\/\/doi.org\/10.1145\/2483028.2483097","relation":{},"subject":[],"published":{"date-parts":[[2013,5,2]]},"assertion":[{"value":"2013-05-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}