{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,25]],"date-time":"2026-03-25T08:43:45Z","timestamp":1774428225455,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":50,"publisher":"ACM","license":[{"start":{"date-parts":[[2013,6,23]],"date-time":"2013-06-23T00:00:00Z","timestamp":1371945600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100006785","name":"Google","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006785","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100007015","name":"University of Wisconsin-Madison","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100007015","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000144","name":"Division of Computer and Network Systems","doi-asserted-by":"publisher","award":["CNS-0720565, CNS-0916725, CNS-1117280, CNS-0834473"],"award-info":[{"award-number":["CNS-0720565, CNS-0916725, CNS-1117280, CNS-0834473"]}],"id":[{"id":"10.13039\/100000144","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2013,6,23]]},"DOI":"10.1145\/2485922.2485943","type":"proceedings-article","created":{"date-parts":[[2013,6,25]],"date-time":"2013-06-25T15:13:21Z","timestamp":1372173201000},"page":"237-248","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":209,"title":["Efficient virtual memory for big memory servers"],"prefix":"10.1145","author":[{"given":"Arkaprava","family":"Basu","sequence":"first","affiliation":[{"name":"University of Wisconsin-Madison, Madison, WI"}]},{"given":"Jayneel","family":"Gandhi","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison, Madison, WI"}]},{"given":"Jichuan","family":"Chang","sequence":"additional","affiliation":[{"name":"Hewlett-Packard Laboratories, Palo Alto, CA"}]},{"given":"Mark D.","family":"Hill","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison, Madison, WI"}]},{"given":"Michael M.","family":"Swift","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison, Madison, WI"}]}],"member":"320","published-online":{"date-parts":[[2013,6,23]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168860"},{"key":"e_1_3_2_1_2_1","volume-title":"Proceedings of the 39th Annual International Symposium on Computer Architecture (Jun.","author":"Ahn J.","year":"2012","unstructured":"Ahn , J. et al. 2012. Revisiting Hardware-Assisted Page Walks for Virtualized Systems . Proceedings of the 39th Annual International Symposium on Computer Architecture (Jun. 2012 ). Ahn, J. et al. 2012. Revisiting Hardware-Assisted Page Walks for Virtualized Systems. Proceedings of the 39th Annual International Symposium on Computer Architecture (Jun. 2012)."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000101"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815970"},{"key":"e_1_3_2_1_5_1","volume-title":"Proceedings of the 39th annual international symposium on Computer architecture (Jun.","author":"Basu A.","year":"2012","unstructured":"Basu , A. et al. 2012. Reducing Memory Reference Energy With Opportunistic Virtual Caching . Proceedings of the 39th annual international symposium on Computer architecture (Jun. 2012 ), 297--308. Basu, A. et al. 2012. Reducing Memory Reference Energy With Opportunistic Virtual Caching. Proceedings of the 39th annual international symposium on Computer architecture (Jun. 2012), 297--308."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1346281.1346286"},{"key":"e_1_3_2_1_7_1","volume-title":"Proc. of the 17th IEEE Symp. on High-Performance Computer Architecture (Feb.","author":"Bhattacharjee A.","year":"2011","unstructured":"Bhattacharjee , A. et al. 2011. Shared last-level TLBs for chip multiprocessors . Proc. of the 17th IEEE Symp. on High-Performance Computer Architecture (Feb. 2011 ). Bhattacharjee, A. et al. 2011. Shared last-level TLBs for chip multiprocessors. Proc. of the 17th IEEE Symp. on High-Performance Computer Architecture (Feb. 2011)."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.26"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736060"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/139669.139708"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.73"},{"key":"e_1_3_2_1_13_1","unstructured":"Couleur J. F. and Glaser E. L. 1968. Shared-access Data Processing System. Nov. 1968.  Couleur J. F. and Glaser E. L. 1968. Shared-access Data Processing System. Nov. 1968."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/363095.363139"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/356571.356573"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/800015.808199"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"e_1_3_2_1_18_1","volume-title":"Proceedings of the annual conference on USENIX Annual Technical Conference","author":"Ganapathy N.","year":"1998","unstructured":"Ganapathy , N. and Schimmel , C . 1998. General purpose operating system support for multiple page sizes . Proceedings of the annual conference on USENIX Annual Technical Conference ( 1998 ). Ganapathy, N. and Schimmel, C. 1998. General purpose operating system support for multiple page sizes. Proceedings of the annual conference on USENIX Annual Technical Conference (1998)."},{"key":"e_1_3_2_1_19_1","unstructured":"graph500 -- The Graph500 List: http:\/\/www.graph500.org\/.  graph500 -- The Graph500 List: http:\/\/www.graph500.org\/."},{"key":"e_1_3_2_1_20_1","unstructured":"Huge Pages\/libhugetlbfs: 2010. http:\/\/lwn.net\/Articles\/374424\/.  Huge Pages\/libhugetlbfs: 2010. http:\/\/lwn.net\/Articles\/374424\/."},{"key":"e_1_3_2_1_21_1","unstructured":"Intel 8086: http:\/\/en.wikipedia.org\/wiki\/Intel_8086.  Intel 8086: http:\/\/en.wikipedia.org\/wiki\/Intel_8086."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.926161"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.710872"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545237"},{"key":"e_1_3_2_1_25_1","unstructured":"Large Page Performance: ESX Server 3.5 and ESX Server 3i v3.5: http:\/\/www.vmware.com\/files\/pdf\/large_pg_performance.pdf.  Large Page Performance: ESX Server 3.5 and ESX Server 3i v3.5: http:\/\/www.vmware.com\/files\/pdf\/large_pg_performance.pdf."},{"key":"e_1_3_2_1_26_1","unstructured":"Linux pmap utility: http:\/\/linux.die.net\/man\/1\/pmap.  Linux pmap utility: http:\/\/linux.die.net\/man\/1\/pmap."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2445572.2445574"},{"key":"e_1_3_2_1_28_1","unstructured":"Marissa Mayer at Web 2.0: http:\/\/glinden.blogspot.com\/2006\/11\/marissa-mayer-at-web-20.html.  Marissa Mayer at Web 2.0: http:\/\/glinden.blogspot.com\/2006\/11\/marissa-mayer-at-web-20.html."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155650"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2008.4510742"},{"key":"e_1_3_2_1_31_1","unstructured":"Memory Hotplug: http:\/\/www.kernel.org\/doc\/Documentation\/memory-hotplug.txt.  Memory Hotplug: http:\/\/www.kernel.org\/doc\/Documentation\/memory-hotplug.txt."},{"key":"e_1_3_2_1_32_1","unstructured":"Microsystems S. 2007. UltraSPARC T2#8482; Supplement to the UltraSPARC Architecture 2007. (Sep. 2007).  Microsystems S. 2007. UltraSPARC T2#8482; Supplement to the UltraSPARC Architecture 2007. (Sep. 2007)."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.5555\/1060289.1060299"},{"key":"e_1_3_2_1_34_1","unstructured":"Oprofile: http:\/\/oprofile.sourceforge.net\/.  Oprofile: http:\/\/oprofile.sourceforge.net\/."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1965724.1965751"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.32"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2011.18"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2391229.2391236"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1346256.1346268"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339666"},{"key":"e_1_3_2_1_41_1","volume-title":"MICRO 2011 Keynote address.","author":"Sodani A.","year":"2011","unstructured":"Sodani , A. 2011 . Race to Exascale: Opportunities and Challenges . MICRO 2011 Keynote address. Sodani, A. 2011. Race to Exascale: Opportunities and Challenges. MICRO 2011 Keynote address."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.26"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/139669.140406"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195531"},{"key":"e_1_3_2_1_45_1","unstructured":"TCMalloc: Thread-Caching Malloc: http:\/\/goog-perftools.sourceforge.net\/doc\/tcmalloc.html.  TCMalloc: Thread-Caching Malloc: http:\/\/goog-perftools.sourceforge.net\/doc\/tcmalloc.html."},{"key":"e_1_3_2_1_46_1","unstructured":"Transparent huge pages: 2011. www.lwn.net\/Articles\/423584\/.  Transparent huge pages: 2011. www.lwn.net\/Articles\/423584\/."},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950379"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.5555\/1060289.1060307"},{"key":"e_1_3_2_1_49_1","volume-title":"Proceedings of 13th annual international symposium on Computer architecture (Jun.","author":"Wood D. A.","year":"1986","unstructured":"Wood , D. A. et al. 1986. An in-cache address translation mechanism . Proceedings of 13th annual international symposium on Computer architecture (Jun. 1986 ). Wood, D. A. et al. 1986. An in-cache address translation mechanism. Proceedings of 13th annual international symposium on Computer architecture (Jun. 1986)."},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/1810085.1810109"}],"event":{"name":"ISCA'13: The 40th Annual International Symposium on Computer Architecture","location":"Tel-Aviv Israel","acronym":"ISCA'13","sponsor":["IEEE CS","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 40th Annual International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2485922.2485943","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2485922.2485943","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:48:43Z","timestamp":1750222123000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2485922.2485943"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,6,23]]},"references-count":50,"alternative-id":["10.1145\/2485922.2485943","10.1145\/2485922"],"URL":"https:\/\/doi.org\/10.1145\/2485922.2485943","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/2508148.2485943","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2013,6,23]]},"assertion":[{"value":"2013-06-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}