{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:23:16Z","timestamp":1750306996243,"version":"3.41.0"},"reference-count":28,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2013,6,1]],"date-time":"2013-06-01T00:00:00Z","timestamp":1370044800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100004963","name":"Seventh Framework Programme","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004963","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2013,6]]},"abstract":"<jats:p>Networks-on-chip need to survive to manufacturing faults in order to sustain yield. An effective testing and configuration strategy however implies two opposite requirements. One one hand, a fast and scalable built-in self-testing and self-diagnosis procedure has to be carried out concurrently at NoC switches. On the other hand, programming the NoC routing mechanism to go around faulty links and switches can be optimally performed by a centralized controller with global network visibility. To the best of our knowledge, this article proposes for the first time a global network testing and configuration strategy that meets the opposite requirements by means of a fault-tolerant dual network architecture and a fast configuration algorithm for the most common failure patterns.<\/jats:p>\n          <jats:p>Experimental results report an area overhead as low as 12.5% with respect to the baseline switch architecture while achieving a high degree of fault tolerance. In fact, even when multiple stuck-at faults are considered, the capability of fault masking by the dual network is always over 80%, and the support for multiple link failures is more than 90% in presence of two unusable links in the main network with minimum set-up times.<\/jats:p>","DOI":"10.1145\/2485984.2485994","type":"journal-article","created":{"date-parts":[[2013,7,1]],"date-time":"2013-07-01T12:27:28Z","timestamp":1372681648000},"page":"1-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs"],"prefix":"10.1145","volume":"12","author":[{"given":"Alberto","family":"Ghiribaldi","sequence":"first","affiliation":[{"name":"University of Ferrara, Italy"}]},{"given":"Daniele","family":"Ludovici","sequence":"additional","affiliation":[{"name":"University of Ferrara, Italy"}]},{"given":"Francisco","family":"Trivi\u00f1o","sequence":"additional","affiliation":[{"name":"Universidad de Castilla-La Mancha, Spain"}]},{"given":"Alessandro","family":"Strano","sequence":"additional","affiliation":[{"name":"University of Ferrara, Italy"}]},{"given":"Jos\u00e9","family":"Flich","sequence":"additional","affiliation":[{"name":"Universitat Polit\u00e8cnica de Val\u00e8ncia, Spain"}]},{"given":"Jos\u00e9 LUIS","family":"S\u00e1nchez","sequence":"additional","affiliation":[{"name":"Universidad de Castilla-La Mancha, Spain"}]},{"given":"Francisco","family":"Alfaro","sequence":"additional","affiliation":[{"name":"Universidad de Castilla-La Mancha, Spain"}]},{"given":"Michele","family":"Favalli","sequence":"additional","affiliation":[{"name":"University of Ferrara, Italy"}]},{"given":"Davide","family":"Bertozzi","sequence":"additional","affiliation":[{"name":"University of Ferrara, Italy"}]}],"member":"320","published-online":{"date-parts":[[2013,7,3]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the East-West Design Test Symposium. 200--203","author":"Alaghi A.","year":"2008","unstructured":"Alaghi , A. , Sedghi , M. , Karimi , N. , Fathy , M. , and Navabi , Z . 2008. Reliable NoC architecture utilizing a robust rerouting algorithm . In Proceedings of the East-West Design Test Symposium. 200--203 . DOI:http:\/\/dx.doi.org\/10.1109\/EWDTS. 2008 .5580142. 10.1109\/EWDTS.2008.5580142 Alaghi, A., Sedghi, M., Karimi, N., Fathy, M., and Navabi, Z. 2008. Reliable NoC architecture utilizing a robust rerouting algorithm. In Proceedings of the East-West Design Test Symposium. 200--203. DOI:http:\/\/dx.doi.org\/10.1109\/EWDTS.2008.5580142."},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the 23rd NORCHIP Conference. 70--73","author":"Ali M.","year":"2005","unstructured":"Ali , M. , Welzl , M. , and Hellebrand , S . 2005. A dynamic routing mechanism for network on chip . In Proceedings of the 23rd NORCHIP Conference. 70--73 . DOI:http:\/\/dx.doi.org\/10.1109\/NORCHP. 2005 . 1596991. 10.1109\/NORCHP.2005 Ali, M., Welzl, M., and Hellebrand, S. 2005. A dynamic routing mechanism for network on chip. In Proceedings of the 23rd NORCHIP Conference. 70--73. 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