{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:23:15Z","timestamp":1750306995964,"version":"3.41.0"},"reference-count":41,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2013,6,1]],"date-time":"2013-06-01T00:00:00Z","timestamp":1370044800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100000781","name":"European Research Council","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000781","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2013,6]]},"abstract":"<jats:p>\n            Many classes of applications require\n            <jats:italic>Quality of Service<\/jats:italic>\n            (QoS) guarantees from the system interconnect. In\n            <jats:italic>Networks-on-Chip<\/jats:italic>\n            (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in the NoC fabric and its interfaces. In this article we present a novel NoC synthesis framework to automatically build networks that meet hard latency constraints of end-to-end traffic streams without requiring specialized hardware for the network components. The hard latency constraints are met by carefully designing the NoC topology and selecting the appropriate routes for flow using lean best-effort network components. We perform experiments on several\n            <jats:italic>System on Chip<\/jats:italic>\n            (SoC) benchmarks. We compared against a topology synthesis method with no support for real-time constraints and we show that the proposed method can produce topologies that can meet significantly tighter worst case latency constraints (on average 44%). We also show that the tightest worst case latency can be provided with little overhead on power consumption (on average 8.5%).\n          <\/jats:p>","DOI":"10.1145\/2485984.2485996","type":"journal-article","created":{"date-parts":[[2013,7,1]],"date-time":"2013-07-01T12:27:28Z","timestamp":1372681648000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Designing best effort networks-on-chip to meet hard latency constraints"],"prefix":"10.1145","volume":"12","author":[{"given":"Ciprian","family":"Seiculescu","sequence":"first","affiliation":[{"name":"EPFL, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dara","family":"Rahmati","sequence":"additional","affiliation":[{"name":"Sharif University of Technology, Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Srinivasan","family":"Murali","sequence":"additional","affiliation":[{"name":"iNoCs, Sarl Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamid","family":"Sarbazi-Azad","sequence":"additional","affiliation":[{"name":"Sharif University of Technology, Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"University of Bologna, Bologna, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giovanni De","family":"Micheli","sequence":"additional","affiliation":[{"name":"EPFL, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,7,3]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966758"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.36"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2003.07.004"},{"volume-title":"Proceedings of the International Symposium on System-on-Chip. 1--4.","author":"Bouhraoua A.","key":"e_1_2_1_4_1","unstructured":"Bouhraoua , A. and Elrabaa , E . 2006. A high-throughput network-on-chip architecture for systems-on-chip interconnect . In Proceedings of the International Symposium on System-on-Chip. 1--4. Bouhraoua, A. and Elrabaa, E. 2006. A high-throughput network-on-chip architecture for systems-on-chip interconnect. In Proceedings of the International Symposium on System-on-Chip. 1--4."},{"key":"e_1_2_1_5_1","doi-asserted-by":"crossref","unstructured":"Cristina Silvano M. L. and Palermo G. 2011. Low Power Networks-on-Chip 1st Ed. Springer.   Cristina Silvano M. L. and Palermo G. 2011. Low Power Networks-on-Chip 1st Ed. Springer.","DOI":"10.1007\/978-1-4419-6911-8"},{"key":"e_1_2_1_6_1","volume-title":"Chips: Technology and Tools (electronic version)","author":"De Micheli G.","year":"2006","unstructured":"De Micheli , G. and Benini , L . 2006 . Networks on Chips: Technology and Tools (electronic version) . Elsevier , Burlington, MA . De Micheli, G. and Benini, L. 2006. Networks on Chips: Technology and Tools (electronic version). Elsevier, Burlington, MA."},{"volume-title":"Proceedings of the IEEE International System-on-Chip Conference. 274--277","author":"Feliciian F.","key":"e_1_2_1_7_1","unstructured":"Feliciian , F. and Furber , S . 2004. An asynchronous on-chip network router with quality-of-service (QoS) support . In Proceedings of the IEEE International System-on-Chip Conference. 274--277 . Feliciian, F. and Furber, S. 2004. An asynchronous on-chip network router with quality-of-service (QoS) support. In Proceedings of the IEEE International System-on-Chip Conference. 274--277."},{"key":"e_1_2_1_8_1","doi-asserted-by":"crossref","unstructured":"Flich J. and Bertozzi D. 2010. Designing Network On-Chip Architectures in the Nanoscale Era. Chapman & Hall\/CRC.   Flich J. and Bertozzi D. 2010. Designing Network On-Chip Architectures in the Nanoscale Era. Chapman & Hall\/CRC.","DOI":"10.1201\/b10477"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.99"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1084834.1084857"},{"key":"e_1_2_1_11_1","doi-asserted-by":"crossref","unstructured":"Hendrickson B. and Leland R. 1994. The Chaco user's guide: Version 2.0. Sandia Tech rep. SAND942692.  Hendrickson B. and Leland R. 1994. The Chaco user's guide: Version 2.0. Sandia Tech rep. SAND942692.","DOI":"10.2172\/10106339"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2006.15"},{"key":"e_1_2_1_13_1","volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe (DATE'03)","volume":"1","author":"Hu J.","unstructured":"Hu , J. and Marculescu , R . 2003. Exploiting the routing flexibility for energy\/performance aware mapping of regular noc architectures . In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'03) . Vol. 1 , IEEE, 10688. Hu, J. and Marculescu, R. 2003. Exploiting the routing flexibility for energy\/performance aware mapping of regular noc architectures. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'03). Vol. 1, IEEE, 10688."},{"volume-title":"Proceedings of the IEEE International System-on-Chip Conference. 289--293","author":"Kavaldjiev N.","key":"e_1_2_1_14_1","unstructured":"Kavaldjiev , N. , Smit , G. , and Jansen , P . 2004. A virtual channel router for on-chip networks . In Proceedings of the IEEE International System-on-Chip Conference. 289--293 . Kavaldjiev, N., Smit, G., and Jansen, P. 2004. A virtual channel router for on-chip networks. In Proceedings of the IEEE International System-on-Chip Conference. 289--293."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.16792"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0743-7315(02)00055-2"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1084834.1084858"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278510"},{"volume-title":"Proceedings of the IEEE International System-on-Chip Conference. 1--4.","author":"Mello A.","key":"e_1_2_1_19_1","unstructured":"Mello , A. , Tedesco , L. , Calazans , N. , and Moraes , F . 2006. Evaluation of current qos mechanisms in networks on chip . In Proceedings of the IEEE International System-on-Chip Conference. 1--4. Mello, A., Tedesco, L., Calazans, N., and Moraes, F. 2006. Evaluation of current qos mechanisms in networks on chip. In Proceedings of the IEEE International System-on-Chip Conference. 1--4."},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe (DATE'04)","volume":"2","author":"Millberg M.","year":"2089","unstructured":"Millberg , M. , Nilsson , E. , Thid , R. , and Jantsch , A . 2004. Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip . In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'04) , Vol. 2 . IEEE, 2089 0--. Millberg, M., Nilsson, E., Thid, R., and Jantsch, A. 2004. Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'04), Vol. 2. IEEE, 20890--."},{"volume-title":"Proceedings of the IEEE International System-on-Chip Conference. 141--142","author":"Mondinelli F.","key":"e_1_2_1_21_1","unstructured":"Mondinelli , F. , Borgatti , M. , and Vajna , Z . 2004. A 0.13 mu;m 1gb\/s\/channel store-and-forward network on-chip . In Proceedings of the IEEE International System-on-Chip Conference. 141--142 . Mondinelli, F., Borgatti, M., and Vajna, Z. 2004. A 0.13 mu;m 1gb\/s\/channel store-and-forward network on-chip. In Proceedings of the IEEE International System-on-Chip Conference. 141--142."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118348"},{"volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe. 20896","author":"Murali S.","key":"e_1_2_1_23_1","unstructured":"Murali , S. and Micheli , G. D . 2004a. Bandwidth-constrained mapping of cores onto noc architectures . In Proceedings of the Conference on Design, Automation and Test in Europe. 20896 . Murali, S. and Micheli, G. D. 2004a. Bandwidth-constrained mapping of cores onto noc architectures. In Proceedings of the Conference on Design, Automation and Test in Europe. 20896."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996809"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120737"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233573"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2008.18"},{"key":"e_1_2_1_28_1","unstructured":"Philips. 2004. Philips nexperia highly integrated programmable system-on-chip (mpsoc). http:\/\/www. semiconductors.philips.com\/products\/nexperia.  Philips. 2004. Philips nexperia highly integrated programmable system-on-chip (mpsoc). http:\/\/www. semiconductors.philips.com\/products\/nexperia."},{"volume-title":"Proceedings of the International Conference on Computer Design. 146","author":"Pinto A.","key":"e_1_2_1_29_1","unstructured":"Pinto , A. , Carloni , L. P. , and Sangiovanni-Vincentelli , A. L . 2003. Efficient synthesis of networks on chip . In Proceedings of the International Conference on Computer Design. 146 . Pinto, A., Carloni, L. P., and Sangiovanni-Vincentelli, A. L. 2003. Efficient synthesis of networks on chip. In Proceedings of the International Conference on Computer Design. 146."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.839493(410) 24"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687507"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20030830"},{"key":"e_1_2_1_33_1","unstructured":"Salminen E. Kulmala A. and H\u00e4m\u00e4l\u00e4inen T. 2008. Survey of network-on-chip proposals. http:\/\/www. ocpip.org.  Salminen E. Kulmala A. and H\u00e4m\u00e4l\u00e4inen T. 2008. Survey of network-on-chip proposals. http:\/\/www. ocpip.org."},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2061610"},{"volume-title":"Proceedings of the 2nd ACM\/IEEE International Symposium on Networks-on-Chip (NOCS'08)","author":"Shi Z.","key":"e_1_2_1_35_1","unstructured":"Shi , Z. and Burns , A . 2008. Real-time communication analysis for on-chip networks with wormhole switching . In Proceedings of the 2nd ACM\/IEEE International Symposium on Networks-on-Chip (NOCS'08) . IEEE, 161--170. Shi, Z. and Burns, A. 2008. Real-time communication analysis for on-chip networks with wormhole switching. In Proceedings of the 2nd ACM\/IEEE International Symposium on Networks-on-Chip (NOCS'08). IEEE, 161--170."},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD'05)","author":"Srinivasan K.","key":"e_1_2_1_36_1","unstructured":"Srinivasan , K. , Chatha , K. S. , and Konjevod , G . 2005. An automated technique for topology and route generation of application specific on-chip interconnection networks . In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD'05) . IEEE, 231--237. Srinivasan, K., Chatha, K. S., and Konjevod, G. 2005. An automated technique for topology and route generation of application specific on-chip interconnection networks. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD'05). IEEE, 231--237."},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.1"},{"key":"e_1_2_1_38_1","unstructured":"STMIcroelectronics. 2004. ST nomadik multimedia processor. http:\/\/www.st.com\/stonline\/prodpres\/dedicate\/proc\/proc.htm.  STMIcroelectronics. 2004. ST nomadik multimedia processor. http:\/\/www.st.com\/stonline\/prodpres\/dedicate\/proc\/proc.htm."},{"key":"e_1_2_1_39_1","unstructured":"TI Instruments. 2004. TI's omap platform. http:\/\/focus.ti.com\/omap\/docs\/.  TI Instruments. 2004. TI's omap platform. http:\/\/focus.ti.com\/omap\/docs\/."},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/1151074.1151076"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774670"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2485984.2485996","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2485984.2485996","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:48:44Z","timestamp":1750236524000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2485984.2485996"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,6]]},"references-count":41,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2013,6]]}},"alternative-id":["10.1145\/2485984.2485996"],"URL":"https:\/\/doi.org\/10.1145\/2485984.2485996","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2013,6]]},"assertion":[{"value":"2011-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-07-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}