{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:23:15Z","timestamp":1750306995686,"version":"3.41.0"},"reference-count":40,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2013,6,1]],"date-time":"2013-06-01T00:00:00Z","timestamp":1370044800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100004085","name":"Ministry of Education, Science and Technology","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004085","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003836","name":"IC Design Education Center","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003836","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2013,6]]},"abstract":"<jats:p>The network-on-chip (NoC) plays a crucial role in memory performance due to the fact that it can handle the majority of traffics from\/to the DRAM memory controllers. However, there has been little work on the interplay between the NoC and memory controllers. In this article, we address a problem called network congestion-induced memory blocking and propose a novel memory controller, which performs memory access scheduling and network entry control in a network congestion-aware manner. In case of network congestion, in order to avoid performance degradation due to the blocking caused by data bound for congested regions in the NoC, the proposed memory controller favors requests and data associated with uncongested regions. In addition, in order to avoid the fairness problem of such a policy, we also propose a gradual method, which enables a trade-off between performance (in memory utilization) and fairness (in memory access latency). Experimental results show that the proposed method can offer up to 1.76 \u223c 2.99 times improvement in memory utilization in the latency-tolerant designs.<\/jats:p>","DOI":"10.1145\/2485984.2485998","type":"journal-article","created":{"date-parts":[[2013,7,1]],"date-time":"2013-07-01T12:27:28Z","timestamp":1372681648000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["A network congestion-aware memory subsystem for manycore"],"prefix":"10.1145","volume":"12","author":[{"given":"Dongki","family":"Kim","sequence":"first","affiliation":[{"name":"POSTECH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sungjoo","family":"Yoo","sequence":"additional","affiliation":[{"name":"POSTECH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sunggu","family":"Lee","sequence":"additional","affiliation":[{"name":"POSTECH"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,7,3]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_2_1_1_1","DOI":"10.1145\/1555754.1555810"},{"doi-asserted-by":"publisher","key":"e_1_2_1_2_1","DOI":"10.1145\/1188455.1188540"},{"doi-asserted-by":"publisher","key":"e_1_2_1_3_1","DOI":"10.1145\/1289816.1289877"},{"unstructured":"Arm Ltd. AMBA3 (AXI) protocol. http:\/\/www.arm.com\/products\/solutions\/AMBAHome Page.html.  Arm Ltd. AMBA3 (AXI) protocol. http:\/\/www.arm.com\/products\/solutions\/AMBAHome Page.html.","key":"e_1_2_1_4_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_5_1","DOI":"10.1145\/1278480.1278667"},{"doi-asserted-by":"publisher","key":"e_1_2_1_6_1","DOI":"10.1109\/71.219761"},{"doi-asserted-by":"publisher","key":"e_1_2_1_7_1","DOI":"10.1109\/NOCS.2010.19"},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of the JEDEC Mobile Memory Forum.","author":"Dumas S.","year":"2011","unstructured":"Dumas , S. 2011 . LPDDR3 and WideIO . In Proceedings of the JEDEC Mobile Memory Forum. Dumas, S. 2011. LPDDR3 and WideIO. In Proceedings of the JEDEC Mobile Memory Forum."},{"volume-title":"Proceedings of the International Symposium on High-Performance Computer Architecture.","author":"Gratz P.","unstructured":"Gratz , P. , Grot , B. , and Keckler , S. W . 2008. Regional congestion awareness for load balance in networks-on-chip . In Proceedings of the International Symposium on High-Performance Computer Architecture. Gratz, P., Grot, B., and Keckler, S. W. 2008. Regional congestion awareness for load balance in networks-on-chip. In Proceedings of the International Symposium on High-Performance Computer Architecture.","key":"e_1_2_1_9_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_10_1","DOI":"10.1145\/1065579.1065729"},{"doi-asserted-by":"publisher","key":"e_1_2_1_11_1","DOI":"10.1109\/MICRO.2004.4"},{"unstructured":"Intel Co. Single-chip cloud computer. http:\/\/techresearch.intel.com\/articles\/Tera-Scale\/1826.htm.  Intel Co. Single-chip cloud computer. http:\/\/techresearch.intel.com\/articles\/Tera-Scale\/1826.htm.","key":"e_1_2_1_12_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_13_1","DOI":"10.1109\/ISCA.2008.21"},{"doi-asserted-by":"publisher","key":"e_1_2_1_14_1","DOI":"10.1145\/1629911.1630117"},{"doi-asserted-by":"publisher","key":"e_1_2_1_15_1","DOI":"10.1145\/1837274.1837387"},{"doi-asserted-by":"publisher","key":"e_1_2_1_16_1","DOI":"10.1109\/NOCS.2010.36"},{"doi-asserted-by":"publisher","key":"e_1_2_1_17_1","DOI":"10.1145\/1065579.1065726"},{"key":"e_1_2_1_18_1","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference.","author":"Kim J-S","year":"2011","unstructured":"Kim , J-S ., Oh , C. , 2011 . 1.2V 12.8GB\/s 2Gb Mobile wide-I\/O DRAM with 4x 128 I\/Os using TSV-based stacking . In Proceedings of the IEEE International Solid-State Circuits Conference. Kim, J-S., Oh, C., et al. 2011. 1.2V 12.8GB\/s 2Gb Mobile wide-I\/O DRAM with 4x 128 I\/Os using TSV-based stacking. In Proceedings of the IEEE International Solid-State Circuits Conference."},{"volume-title":"Proceedings of the International Symposium on High-Performance Computer Architecture.","author":"Kim Y.","unstructured":"Kim , Y. , Han , D. , Mutlu , O. , and Harchol-Balter , M . 2010b. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers . In Proceedings of the International Symposium on High-Performance Computer Architecture. Kim, Y., Han, D., Mutlu, O., and Harchol-Balter, M. 2010b. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. In Proceedings of the International Symposium on High-Performance Computer Architecture.","key":"e_1_2_1_19_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_20_1","DOI":"10.1145\/1250662.1250681"},{"doi-asserted-by":"publisher","key":"e_1_2_1_21_1","DOI":"10.1145\/1403375.1403677"},{"doi-asserted-by":"publisher","key":"e_1_2_1_22_1","DOI":"10.1145\/1391469.1391585"},{"volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe.","author":"Kwon W.","unstructured":"Kwon , W. and Yoo , S . 2009. In-network reorder buffer to improve NoC performance while resolving the in-order requirement problem . In Proceedings of the Conference on Design, Automation and Test in Europe. Kwon, W. and Yoo, S. 2009. In-network reorder buffer to improve NoC performance while resolving the in-order requirement problem. In Proceedings of the Conference on Design, Automation and Test in Europe.","key":"e_1_2_1_23_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_24_1","DOI":"10.1109\/MICRO.2008.4771791"},{"unstructured":"Lee H. 2010. 3D stacked memory design. In Proceding of the 3D IC Workshop.  Lee H. 2010. 3D stacked memory design. In Proceding of the 3D IC Workshop.","key":"e_1_2_1_25_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_26_1","DOI":"10.1109\/MM.2008.31"},{"doi-asserted-by":"publisher","key":"e_1_2_1_27_1","DOI":"10.1109\/ISCA.2008.15"},{"unstructured":"Lx2 Tensilica Ltd. 2010. Xtensa customizable processors. http:\/\/www.tensilica.com\/products\/xtensa-customizable.htm.  Lx2 Tensilica Ltd. 2010. Xtensa customizable processors. http:\/\/www.tensilica.com\/products\/xtensa-customizable.htm.","key":"e_1_2_1_28_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_29_1","DOI":"10.1145\/2000064.2000074"},{"doi-asserted-by":"publisher","key":"e_1_2_1_30_1","DOI":"10.1109\/MICRO.2007.40"},{"volume-title":"Proceedings of the International Symposium on Computer Architecture.","author":"Mutlu O.","unstructured":"Mutlu , O. and Moscibroda , T . 2008. Parallelism-aware memory access scheduling . In Proceedings of the International Symposium on Computer Architecture. Mutlu, O. and Moscibroda, T. 2008. Parallelism-aware memory access scheduling. In Proceedings of the International Symposium on Computer Architecture.","key":"e_1_2_1_31_1"},{"volume-title":"Proceedings of the International Symposium on High-Performance Computer Architecture.","author":"Peh L.","unstructured":"Peh , L. and Dally , W. J . 2001. A delay model and speculative architecture for pipelined routers . In Proceedings of the International Symposium on High-Performance Computer Architecture. Peh, L. and Dally, W. J. 2001. A delay model and speculative architecture for pipelined routers. In Proceedings of the International Symposium on High-Performance Computer Architecture.","key":"e_1_2_1_32_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_33_1","DOI":"10.1145\/115952.115961"},{"doi-asserted-by":"publisher","key":"e_1_2_1_34_1","DOI":"10.1145\/339647.339668"},{"doi-asserted-by":"publisher","key":"e_1_2_1_35_1","DOI":"10.1145\/859618.859641"},{"doi-asserted-by":"publisher","key":"e_1_2_1_36_1","DOI":"10.1109\/L-CA.2004.8"},{"doi-asserted-by":"publisher","key":"e_1_2_1_37_1","DOI":"10.1109\/12.192212"},{"volume-title":"Proceedings of the International Symposium on High Performance Computer Architecture.","author":"Woo D.","unstructured":"Woo , D. , Seong , N. , Lewis , D. L. , and Lee , H . 2010. An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth . In Proceedings of the International Symposium on High Performance Computer Architecture. Woo, D., Seong, N., Lewis, D. L., and Lee, H. 2010. An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth. In Proceedings of the International Symposium on High Performance Computer Architecture.","key":"e_1_2_1_38_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_39_1","DOI":"10.1145\/360128.360134"},{"doi-asserted-by":"publisher","key":"e_1_2_1_40_1","DOI":"10.1109\/HPCA.2005.2"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2485984.2485998","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2485984.2485998","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:48:44Z","timestamp":1750236524000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2485984.2485998"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,6]]},"references-count":40,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2013,6]]}},"alternative-id":["10.1145\/2485984.2485998"],"URL":"https:\/\/doi.org\/10.1145\/2485984.2485998","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2013,6]]},"assertion":[{"value":"2011-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-07-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}