{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:21:18Z","timestamp":1750306878921,"version":"3.41.0"},"reference-count":22,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2013,10,1]],"date-time":"2013-10-01T00:00:00Z","timestamp":1380585600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100003176","name":"Ministerio de Educaci\u00f3n, Cultura y Deporte","doi-asserted-by":"publisher","award":["TIN2006-01078"],"award-info":[{"award-number":["TIN2006-01078"]}],"id":[{"id":"10.13039\/501100003176","id-type":"DOI","asserted-by":"publisher"}]},{"name":"University CEU San Pablo and Banco Santander","award":["USP-BS PPC05\/2010"],"award-info":[{"award-number":["USP-BS PPC05\/2010"]}]},{"DOI":"10.13039\/501100011011","name":"Junta of Andaluc\u00eda","doi-asserted-by":"crossref","award":["P07-TIC-02630"],"award-info":[{"award-number":["P07-TIC-02630"]}],"id":[{"id":"10.13039\/501100011011","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2013,10]]},"abstract":"<jats:p>Constant multipliers are widely used in signal processing applications to implement the multiplication of signals by a constant coefficient. However, in some applications, this coefficient remains invariable only during an interval of time, and then, its value changes to adapt to new circumstances. In this article, we present a self-reconfigurable constant multiplier suitable for LUT-based FPGAs able to reload the constant in runtime. The pipelined architecture presented is easily scalable to any multiplicand and constant sizes, for unsigned and signed representations. It can be reprogrammed in 16 clock cycles, equivalent to less than 100 ns in current FPGAs. This value is significantly smaller than FPGA partial configuration times. The presented approach is more efficient in terms of area and speed when compared to generic multipliers, achieving up to 91% area reduction and up to 102% speed improvement for the case-study circuits tested. The power consumption of the proposed multipliers are in the range of those of slice-based multipliers provided by the vendor.<\/jats:p>","DOI":"10.1145\/2490830","type":"journal-article","created":{"date-parts":[[2013,10,17]],"date-time":"2013-10-17T12:23:34Z","timestamp":1382012614000},"page":"1-17","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Self-Reconfigurable Constant Multiplier for FPGA"],"prefix":"10.1145","volume":"6","author":[{"given":"Javier","family":"Hormigo","sequence":"first","affiliation":[{"name":"Universidad de M\u00e1laga"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gabriel","family":"Caffarena","sequence":"additional","affiliation":[{"name":"Universidad CEU San Pablo"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Juan P.","family":"Oliver","sequence":"additional","affiliation":[{"name":"Universidad de la Rep\u00fablica"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eduardo","family":"Boemo","sequence":"additional","affiliation":[{"name":"Universidad Aut\u00f3noma de Madrid"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,10]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_2_1_1_1","DOI":"10.1109\/92.784091"},{"doi-asserted-by":"publisher","key":"e_1_2_1_2_1","DOI":"10.1145\/1462586.1462593"},{"doi-asserted-by":"publisher","key":"e_1_2_1_3_1","DOI":"10.1155\/2009\/703267"},{"volume-title":"\u201cxc4000e\u201d. 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Circuits Syst. II 54, 11, 974--978. Gustafsson, O. 2007. Lower bounds for constant multiplication problems. IEEE Trans. Circuits Syst. II 54, 11, 974--978.","journal-title":"IEEE Trans. Circuits Syst."},{"doi-asserted-by":"publisher","key":"e_1_2_1_10_1","DOI":"10.1007\/s00034-005-2505-5"},{"doi-asserted-by":"publisher","key":"e_1_2_1_11_1","DOI":"10.1109\/TVLSI.2007.912042"},{"doi-asserted-by":"publisher","key":"e_1_2_1_12_1","DOI":"10.1109\/TVLSI.2009.2014068"},{"doi-asserted-by":"publisher","key":"e_1_2_1_13_1","DOI":"10.1109\/TCAD.2009.2035548"},{"doi-asserted-by":"publisher","key":"e_1_2_1_14_1","DOI":"10.1109\/VLSISOC.2010.5642660"},{"doi-asserted-by":"publisher","key":"e_1_2_1_15_1","DOI":"10.1109\/92.863621"},{"volume-title":"Proceedings of the Southern Conference on Programmable Logic. 87--90","author":"Oliver J.","unstructured":"Oliver , J. and Boemo , E . 2011. Power estimations vs. power measurements in Cyclone III devices . In Proceedings of the Southern Conference on Programmable Logic. 87--90 . Oliver, J. and Boemo, E. 2011. Power estimations vs. power measurements in Cyclone III devices. In Proceedings of the Southern Conference on Programmable Logic. 87--90.","key":"e_1_2_1_16_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_17_1","DOI":"10.1109\/JSSC.2003.821785"},{"doi-asserted-by":"publisher","key":"e_1_2_1_18_1","DOI":"10.1109\/TC.2010.115"},{"doi-asserted-by":"publisher","key":"e_1_2_1_19_1","DOI":"10.1109\/TVLSI.2004.833399"},{"key":"e_1_2_1_20_1","volume-title":"Field-Programmable Logic and Application. Lecture Notes in Computer Science","volume":"3203","author":"Wilton S.","unstructured":"Wilton , S. , Ang , S. , and Luk , W . 2004. The impact of pipelining on energy per operation in field-programmable gate arrays . In Field-Programmable Logic and Application. Lecture Notes in Computer Science , Vol. 3203 . Springer-Verlag, Berlin, 719--728. Wilton, S., Ang, S., and Luk, W. 2004. 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