{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:19:25Z","timestamp":1750306765846,"version":"3.41.0"},"reference-count":33,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2013,7,1]],"date-time":"2013-07-01T00:00:00Z","timestamp":1372636800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100004963","name":"Seventh Framework Programme","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004963","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2013,7]]},"abstract":"<jats:p>\n            Dynamic circuit specialization (DCS) is a technique used to implement FPGA applications where some of the input data, called parameters, change slowly compared to other inputs. Each time the parameter values change, the FPGA is reconfigured by a configuration that is specialized for those new parameter values. This specialized configuration is much smaller and faster than a regular configuration. However, the overhead associated with the specialization process should be minimized to achieve the desired benefits of using the DCS technique. This overhead is represented by both the FPGA resources needed to specialize the FPGA at runtime and by the specialization time. The introduction of\n            <jats:italic>parameterized configurations<\/jats:italic>\n            [Bruneel and Stroobandt 2008] has improved the efficiency of DCS implementations. However, the specialization overhead still takes a considerable amount of resources and time.\n          <\/jats:p>\n          <jats:p>In this article, we explore how to efficiently build DCS systems by presenting a variety of possible solutions for the specialization process and the overhead associated with each of them. We split the specialization process into two main phases: the evaluation and the configuration phase. The PowerPC embedded processor, the MicroBlaze, and a customized processor (CP) are used as alternatives in the evaluation phase. In the configuration phase, the ICAP and a custom configuration interface (SRL configuration) are used as alternatives. Each solution is used to implement a DCS system for three applications: an adaptive finite impulse response (FIR) filter, a ternary content-addressable memory (TCAM), and a regular expression matcher (RegEx). The experiments show that the use of our CP along with the SRL configuration achieves minimum overhead in terms of resources and time. Our CP is 1.8 and 3.5 times smaller than the PowerPC and the area-optimized implementation of the MicroBlaze, respectively. Moreover, the use of the CP enables a more compact representation for the parameterized configuration in comparison to both the PowerPC and the MicroBlaze processors. For instance, in the FIR, the parameterized configuration compiled for our CP is 6--7 times smaller than that for the embedded processors.<\/jats:p>","DOI":"10.1145\/2491477.2491479","type":"journal-article","created":{"date-parts":[[2013,7,25]],"date-time":"2013-07-25T19:12:41Z","timestamp":1374779561000},"page":"1-38","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["How to efficiently implement dynamic circuit specialization systems"],"prefix":"10.1145","volume":"18","author":[{"given":"Fatma","family":"Abouelella","sequence":"first","affiliation":[{"name":"Ghent University, Ghent, Belgium"}]},{"given":"Tom","family":"Davidson","sequence":"additional","affiliation":[{"name":"Ghent University, Ghent, Belgium"}]},{"given":"Wim","family":"Meeus","sequence":"additional","affiliation":[{"name":"Ghent University, Ghent, Belgium"}]},{"given":"Karel","family":"Bruneel","sequence":"additional","affiliation":[{"name":"Ghent University, Ghent, Belgium"}]},{"given":"Dirk","family":"Stroobandt","sequence":"additional","affiliation":[{"name":"Ghent University, Ghent, Belgium"}]}],"member":"320","published-online":{"date-parts":[[2013,7,29]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.18"},{"key":"e_1_2_1_2_1","unstructured":"Abouelella F. Bruneel K. and Stroobandt D. 2010b. Towards a more efficient run-time FPGA configuration generation. In Parallel Computing: From Multicores and GPU's to Petascale. IOS Press Amsterdam 624--631.  Abouelella F. Bruneel K. and Stroobandt D. 2010b. Towards a more efficient run-time FPGA configuration generation. In Parallel Computing: From Multicores and GPU's to Petascale. IOS Press Amsterdam 624--631."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723175"},{"volume-title":"Application note 119: Implementing high-speed search applications with Altera CAM","author":"Altera","key":"e_1_2_1_4_1","unstructured":"Altera . 2001. Application note 119: Implementing high-speed search applications with Altera CAM . Altera , San Jose, CA . Altera. 2001. Application note 119: Implementing high-speed search applications with Altera CAM. Altera, San Jose, CA."},{"volume-title":"FPGA run-time reconfiguration: Two approaches","author":"Altera","key":"e_1_2_1_5_1","unstructured":"Altera . 2008. FPGA run-time reconfiguration: Two approaches . Altera , San Jose, CA . Altera. 2008. FPGA run-time reconfiguration: Two approaches. Altera, San Jose, CA."},{"key":"e_1_2_1_6_1","unstructured":"Altera. 2009. Interfacing an external processor to an Altera FPGA. Altera SanJose CA.  Altera. 2009. Interfacing an external processor to an Altera FPGA. Altera SanJose CA."},{"volume-title":"Proceedings of the 18th International Conference on Microelectronics (ICM).","author":"Anderson I.","key":"e_1_2_1_7_1","unstructured":"Anderson , I. and Khalid , M . 2006. Soft-core processors for embedded systems . In Proceedings of the 18th International Conference on Microelectronics (ICM). Anderson, I. and Khalid, M. 2006. Soft-core processors for embedded systems. In Proceedings of the 18th International Conference on Microelectronics (ICM)."},{"volume-title":"Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPD'06)","author":"Baker Z. K.","key":"e_1_2_1_8_1","unstructured":"Baker , Z. K. , jip Jung , H. , and Prasanna , V. K . 2006. Regular expression software deceleration for intrusion detection systems . In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPD'06) . Baker, Z. K., jip Jung, H., and Prasanna, V. K. 2006. Regular expression software deceleration for intrusion detection systems. In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPD'06)."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1016\/0095-8956(79)90021-2"},{"volume-title":"Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications","author":"Bobda C.","key":"e_1_2_1_10_1","unstructured":"Bobda , C. 2007. Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications . Springer , Berlin Heidelberg . Bobda, C. 2007. Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications. Springer, Berlin Heidelberg."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1150019.1136500"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2003695.2003703"},{"volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications, U. Kebschull, M. Platzner, and T. J., Eds. Kirchhoff Institute for Physics","author":"Bruneel K.","key":"e_1_2_1_13_1","unstructured":"Bruneel , K. and Stroobandt , D . 2008. Automatic generation of run-time parameterizable configurations . In Proceedings of the International Conference on Field Programmable Logic and Applications, U. Kebschull, M. Platzner, and T. J., Eds. Kirchhoff Institute for Physics , Heidelberg, 361--366. Bruneel, K. and Stroobandt, D. 2008. Automatic generation of run-time parameterizable configurations. In Proceedings of the International Conference on Field Programmable Logic and Applications, U. Kebschull, M. Platzner, and T. J., Eds. Kirchhoff Institute for Physics, Heidelberg, 361--366."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1137\/0608002"},{"key":"e_1_2_1_15_1","unstructured":"Ditech Networks. 2011. Echo basics tutorial. Ditech Networks http:\/\/www.ditechnetworks.com.  Ditech Networks. 2011. Echo basics tutorial. Ditech Networks http:\/\/www.ditechnetworks.com."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2008.4580165"},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the Embedded Training Program Embedded Systems Conference.","author":"Fletcher B. H.","year":"2005","unstructured":"Fletcher , B. H. 2005 . FPGA embedded processors . In Proceedings of the Embedded Training Program Embedded Systems Conference. Fletcher, B. H. 2005. FPGA embedded processors. In Proceedings of the Embedded Training Program Embedded Systems Conference."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1993.279467"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1137\/S0097539795280287"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1137\/S0097539795291550"},{"key":"e_1_2_1_21_1","unstructured":"IBM. 2006. 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In Proceedings of the International Workshop on Logic & Synthesis (IWLS'06)."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864128"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/512760.512784"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/273791"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/954587.954594"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/258305.258316"},{"key":"e_1_2_1_31_1","unstructured":"Xilinx. 2010. Partial reconfiguration user guide. Xilinx UG702: http:\/\/www.xilinx.com\/tools\/partial-reconfiguration.htm.  Xilinx. 2010. Partial reconfiguration user guide. Xilinx UG702: http:\/\/www.xilinx.com\/tools\/partial-reconfiguration.htm."},{"key":"e_1_2_1_32_1","unstructured":"Xilinx. 2000. Benefits of using Xilinx FPGAs with MIPS microprocessors. Xilinx http:\/\/www.xilinx.com\/ipcenter\/processor_central\/wp121.pdf.  Xilinx. 2000. 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