{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T16:05:27Z","timestamp":1780675527510,"version":"3.54.1"},"reference-count":19,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2013,7,1]],"date-time":"2013-07-01T00:00:00Z","timestamp":1372636800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council Taiwan","doi-asserted-by":"publisher","award":["NSC1002220E009045"],"award-info":[{"award-number":["NSC1002220E009045"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2013,7]]},"abstract":"<jats:p>In this article, we propose a flip-flop merging algorithm based on agglomerative clustering. Compared to previous state-of-the-art on flip-flop merging, our proposed algorithm outperforms that of Chang et al. [2010] and Wang et al. [2011] in all aspects, including number of flip-flop reductions, increase in signal wirelength, displacement of flip-flops, and execution time. Our proposed algorithm also has minimal disruption to original placement. In comparison with Jiang et al. [2011], Wang et al. [2011], and Chang et al. [2010], our proposed algorithm has the least displacement when relocating merged flip-flops. While previous works on flip-flop merging focus on the number of flip-flop reduction, we further evaluate the power consumption of clock tree after flip-flop merging. To further minimize clock tree wirelength, we propose a framework that determines a preferable location for relocated merged flip-flops for clock tree synthesis (CTS). Experimental results show that our CTS-driven flip-flop merging can reduce clock tree wirelength by an average of 7.82% with minimum clock network power consumption compared to all of the previous works.<\/jats:p>","DOI":"10.1145\/2491477.2491484","type":"journal-article","created":{"date-parts":[[2013,7,25]],"date-time":"2013-07-25T19:12:41Z","timestamp":1374779561000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization"],"prefix":"10.1145","volume":"18","author":[{"given":"Sean Shih-Ying","family":"Liu","sequence":"first","affiliation":[{"name":"National Chiao Tung University, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wan-Ting","family":"Lo","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company, Limited (TSMC)"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chieh-Jui","family":"Lee","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hung-Ming","family":"Chen","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2013,7,29]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160945"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the International Conference on Computer Aided Design. 218--223","author":"Chang Y.-T.","unstructured":"Chang , Y.-T. , Hsu , C. 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