{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:05:11Z","timestamp":1761581111503,"version":"3.41.0"},"reference-count":40,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2013,7,1]],"date-time":"2013-07-01T00:00:00Z","timestamp":1372636800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61170063 and 60910003"],"award-info":[{"award-number":["61170063 and 60910003"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004708","name":"National Education Ministry","doi-asserted-by":"crossref","award":["20111081042"],"award-info":[{"award-number":["20111081042"]}],"id":[{"id":"10.13039\/501100004708","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2013,7]]},"abstract":"<jats:p>Testing for small-delay defects (SDDs) requires fault-effect propagation along the longest testable paths. However, identification of the longest testable paths requires high CPU time, and the sensitization of all such paths leads to large pattern counts. Dynamic test compaction for small-delay defects is therefore necessary to reduce test-data volume. We present a new technique for identifying the longest testable paths through each gate in order to accelerate test generation for SDDs. The resulting test patterns sensitize the longest testable paths that pass through each SDD site. An efficient dynamic test compaction method based on structural analysis is presented to reduce the pattern count substantially, while ensuring that all the longest paths for each SDD are sensitized. Simulation results for a set of ISCAS 89 and IWLS 05 benchmark circuits demonstrate the effectiveness of this method.<\/jats:p>","DOI":"10.1145\/2491477.2491488","type":"journal-article","created":{"date-parts":[[2013,7,25]],"date-time":"2013-07-25T19:12:41Z","timestamp":1374779561000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":29,"title":["Test compaction for small-delay defects using an effective path selection scheme"],"prefix":"10.1145","volume":"18","author":[{"given":"Dong","family":"Xiang","sequence":"first","affiliation":[{"name":"Tsinghua University, China"}]},{"given":"Jianbo","family":"Li","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[{"name":"Duke University, Durham, NC"}]},{"given":"Xijiang","family":"Lin","sequence":"additional","affiliation":[{"name":"Mentor Graphics Corp, Wilsonville, OR"}]}],"member":"320","published-online":{"date-parts":[[2013,7,29]]},"reference":[{"volume-title":"Proceedings of the Internatioanl Test Conference, 191--200","author":"Chen W. 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Accurate measurement of small delay defect coverage of test patterns . In Proceedings of the International Test Conference. Devta-Prasanna, N., Goel, S. K., Gunda, A., Ward, A., and Krishnamurthy, P. 2009. Accurate measurement of small delay defect coverage of test patterns. In Proceedings of the International Test Conference."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.28"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2010.59"},{"volume-title":"Proceedings of the International Test Conference, 1053--1060","author":"Gupta P.","key":"e_1_2_1_9_1","unstructured":"Gupta , P. and Hsiao , M. S . 2004. ALAPTF: A new transition fault model and the ATPG algorithm . In Proceedings of the International Test Conference, 1053--1060 . Gupta, P. and Hsiao, M. S. 2004. ALAPTF: A new transition fault model and the ATPG algorithm. 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In Proceedings of the International Test Conference. Kajihara, S., Morishima, S., Takuma, A., Wen, X., Maeda, T., Hamada, S., and Sato, Y. 2006. A framework of high-quality transition fault ATPG for scan circuits. In Proceedings of the International Test Conference."},{"volume-title":"Proceedings of the International Test Conference.","author":"Li B.","key":"e_1_2_1_13_1","unstructured":"Li , B. , Fang , L. , and Hsiao , M . 2007. Efficient power droop aware delay fault testing . In Proceedings of the International Test Conference. Li, B., Fang, L., and Hsiao, M. 2007. Efficient power droop aware delay fault testing. In Proceedings of the International Test Conference."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/1191824.1192146"},{"volume-title":"Proceedings of the 16th Asian Test Symposium. 487--492","author":"Lin X.","key":"e_1_2_1_15_1","unstructured":"Lin , X. , Kassab , M. , and Rajski , J ., 2007. Test generation for timing-critical transition faults . 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