{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,15]],"date-time":"2026-01-15T03:33:36Z","timestamp":1768448016804,"version":"3.49.0"},"reference-count":40,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2013,9,1]],"date-time":"2013-09-01T00:00:00Z","timestamp":1377993600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100004963","name":"Seventh Framework Programme","doi-asserted-by":"publisher","award":["ERC-2009-AdG-246810"],"award-info":[{"award-number":["ERC-2009-AdG-246810"]}],"id":[{"id":"10.13039\/501100004963","id-type":"DOI","asserted-by":"publisher"}]},{"name":"ST-IBM-LETI alliance program"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2013,9]]},"abstract":"<jats:p>3D Monolithic Integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. In 3DMI technology the 3D contacts, connecting different active layers, are in the order of few 100nm. Given the advantage of such small contacts, 3DMI enables fine-grain (gate-level) partitioning of circuits. In this work we present three cell transformation techniques for standard cell-based ICs with 3DMI technology. As a major contribution of this work, we propose a design flow comprising of a cell transformation technique,<jats:italic>cell-on-cell stacking<\/jats:italic>, and a physical design technique (CELONCEL<jats:sub>PD<\/jats:sub>) aimed at placing cells transformed with<jats:italic>cell-on-cell<\/jats:italic>stacking. We analyze and compare various cell transformation techniques for 3DMI technology without disrupting the regularity of the IC design flow. Our experiments demonstrate the effectiveness of CELONCEL design technique, yielding us an area reduction of 37.5%, 16.2% average reduction in wirelength, and 6.2% average improvement in overall delay, compared with a 2D case when benchmarked across various designs in 45nm technology node.<\/jats:p>","DOI":"10.1145\/2491675","type":"journal-article","created":{"date-parts":[[2013,10,3]],"date-time":"2013-10-03T13:37:30Z","timestamp":1380807450000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Cell transformations and physical design techniques for 3D monolithic integrated circuits"],"prefix":"10.1145","volume":"9","author":[{"given":"Shashikanth","family":"Bobba","sequence":"first","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland"}]},{"given":"Ashutosh","family":"Chakraborty","sequence":"additional","affiliation":[{"name":"Oracle Microelectronics"}]},{"given":"Olivier","family":"Thomas","sequence":"additional","affiliation":[{"name":"CEA-LETI, France"}]},{"given":"Perrine","family":"Batude","sequence":"additional","affiliation":[{"name":"CEA-LETI, France"}]},{"given":"Giovanni de","family":"Micheli","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland"}]}],"member":"320","published-online":{"date-parts":[[2013,10,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1149\/1.2982853"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2008.4567296"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424352"},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the Symposium on VLSI Technology. 166--167","author":"Batude P.","year":"2009"},{"key":"e_1_2_1_5_1","volume-title":"Proceedings of the IEEE Symposium on VLSI Technology. 158--159","author":"Batude P.","year":"2011"},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the IEEE International 3D Systems Integration Conference (3DIC'10)","author":"Bobba S.","year":"2010"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/1950815.1950889"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630029"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123055"},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'07)","author":"Cong J."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1119772.1119783"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/369691.369763"},{"key":"e_1_2_1_13_1","unstructured":"Encounter. 2013. SOC encounter tool. http:\/\/www.cadence.com\/products\/di\/soc_encounter\/pages\/default.aspx. Encounter. 2013. SOC encounter tool. http:\/\/www.cadence.com\/products\/di\/soc_encounter\/pages\/default.aspx."},{"key":"e_1_2_1_14_1","unstructured":"Gurobi. 2013. Gurobi optimization. http:\/\/www.gurobi.com\/. Gurobi. 2013. Gurobi optimization. http:\/\/www.gurobi.com\/."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929646"},{"key":"e_1_2_1_16_1","volume-title":"Proceedings of the IEEE Custom Integrated Circuits Conference. 207--213","author":"Ieong M."},{"key":"e_1_2_1_17_1","unstructured":"ITC99. 1999. http:\/\/www.cerc.utexas.edu\/itc99-benchmarks\/bendoc1.html. ITC99. 1999. http:\/\/www.cerc.utexas.edu\/itc99-benchmarks\/bendoc1.html."},{"key":"e_1_2_1_18_1","unstructured":"Itrs. 2009. www.itrs.net\/Links\/2009ITRS\/2009Chapters_2009Tables. Itrs. 2009. www.itrs.net\/Links\/2009ITRS\/2009Chapters_2009Tables."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123056"},{"key":"e_1_2_1_20_1","doi-asserted-by":"crossref","unstructured":"Jung S.-M Jang J. Cho W. Moon J. Kwak K. etal 2004. The revolutionary and truly 3-dimensional 25f2 sram technology with the smallest s3 (stacked single-crystal si) cell 0.16um2 and sstft (stacked single-crystal thin film transistor) for ultra high density sram. In Proceedings of the Symposium on VLSI Technology Digest of Technical Papers. 228--229. Jung S.-M Jang J. Cho W. Moon J. Kwak K. et al. 2004. The revolutionary and truly 3-dimensional 25f2 sram technology with the smallest s3 (stacked single-crystal si) cell 0.16um2 and sstft (stacked single-crystal thin film transistor) for ultra high density sram. In Proceedings of the Symposium on VLSI Technology Digest of Technical Papers. 228--229.","DOI":"10.1109\/VLSIT.2004.1345495"},{"key":"e_1_2_1_21_1","volume-title":"Proceedings of the Symposium on VLSI Technology. 68--69","author":"Jung S.-M.","year":"2007"},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the International Conference on Solid State Device and Materials (SSDM'02)","author":"Kim H. S."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687524"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2008.5388565"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887920"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.59"},{"key":"e_1_2_1_27_1","unstructured":"Mentor. 2013. Calibre xrc. http:\/\/www.mentor.com\/products\/ic_nanometer_design\/verification-signoff\/circuit-verification\/calibre-xrc\/. Mentor. 2013. Calibre xrc. http:\/\/www.mentor.com\/products\/ic_nanometer_design\/verification-signoff\/circuit-verification\/calibre-xrc\/."},{"key":"e_1_2_1_28_1","unstructured":"Mit. 2013. 3D Design Kits version 3DEM. Mit. 2013. 3D Design Kits version 3DEM."},{"key":"e_1_2_1_29_1","unstructured":"Nangate. 2013. 45nm library. http:\/\/www.nangate.com\/. Nangate. 2013. 45nm library. http:\/\/www.nangate.com\/."},{"key":"e_1_2_1_30_1","unstructured":"Opencores. 2013. www.opencores.org. Opencores. 2013. www.opencores.org."},{"key":"e_1_2_1_31_1","unstructured":"Pavlidis V. and Friedman E. 2009. Three-Dimensional Integrated Circuit Design. Morgan Kaufmann. Pavlidis V. and Friedman E. 2009. Three-Dimensional Integrated Circuit Design. Morgan Kaufmann."},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055184"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPFA.2010.5532301"},{"key":"e_1_2_1_34_1","unstructured":"Sdc. 2013. Synopsys design compiler. http:\/\/www.synopsys.com\/home.aspx. Sdc. 2013. Synopsys design compiler. http:\/\/www.synopsys.com\/home.aspx."},{"key":"e_1_2_1_35_1","volume-title":"Proceedings of the IEEE International Electron Devices Meeting (IEDM'08)","author":"Sillon N."},{"key":"e_1_2_1_36_1","volume-title":"Proceedings of the IEEE Symposium on VLSI Technology, Digest of Technical Papers. 80--81","author":"Son Y.-H.","year":"2007"},{"key":"e_1_2_1_37_1","unstructured":"Tezzaron. 2013. Wafer stack with super contacts. http:\/\/www.tezzaron.com\/about\/PhotoAlbum\/Products\/Wafer_Pair_Super-Contacts.html. Tezzaron. 2013. Wafer stack with super contacts. http:\/\/www.tezzaron.com\/about\/PhotoAlbum\/Products\/Wafer_Pair_Super-Contacts.html."},{"key":"e_1_2_1_38_1","volume-title":"Proceedings of the International Symposium on VLSI Technology, Systems and Applications. 1--4.","author":"Wong S."},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/785411.785414"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.888266"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2491675","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2491675","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:39:22Z","timestamp":1750235962000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2491675"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":40,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2013,9]]}},"alternative-id":["10.1145\/2491675"],"URL":"https:\/\/doi.org\/10.1145\/2491675","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"value":"1550-4832","type":"print"},{"value":"1550-4840","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,9]]},"assertion":[{"value":"2011-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-06-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-10-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}