{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:16:07Z","timestamp":1763468167129,"version":"3.41.0"},"reference-count":44,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2013,9,1]],"date-time":"2013-09-01T00:00:00Z","timestamp":1377993600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2013,9]]},"abstract":"<jats:p>Improving the vulnerability to soft errors is one of the important design goals for future architecture design of Chip-MultiProcessors (CMPs). In this study, we explore the soft error characteristics of CMPs with 3D stacked NonVolatile Memory (NVM), in particular, the Spin-Transfer Torque Random Access Memory (STT-RAM), whose cells are immune to radiation-induced soft errors and do not have endurance problems. We use 3D stacking as an enabler for modular integration of STT-RAM memories with minimum disruption in the baseline processor design flow, while providing further interconnection and capacity advantages. We take an in-depth look at alternative replacement schemes to explore the soft error resilience benefits and design trade-offs of 3D stacked STT-RAM and capture the multivariable optimization challenges microprocessor architectures face. We propose a vulnerability metric, with respect to the instruction and data in the core pipeline and through the cache hierarchy, to present a comprehensive system evaluation with respect to reliability, performance, and power consumption for our CMP architectures. Our experimental results show that, for the average workload, replacing memories with an STT-RAM alternative significantly mitigates soft errors on-chip, improves the performance by 14.15%, and reduces power consumption by 13.44%.<\/jats:p>","DOI":"10.1145\/2491679","type":"journal-article","created":{"date-parts":[[2013,10,3]],"date-time":"2013-10-03T13:37:30Z","timestamp":1380807450000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory"],"prefix":"10.1145","volume":"9","author":[{"given":"Guangyu","family":"Sun","sequence":"first","affiliation":[{"name":"The Pennsylvania State University, PA"}]},{"given":"Eren","family":"Kursun","sequence":"additional","affiliation":[{"name":"IBM TJ Watson Research Center, NY"}]},{"given":"Jude A.","family":"Rivers","sequence":"additional","affiliation":[{"name":"IBM TJ Watson Research Center, NY"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, PA"}]}],"member":"320","published-online":{"date-parts":[[2013,10,8]]},"reference":[{"volume-title":"Proceedings of the 43rd IEEE International Annual Reliability Physics Symposium. 163--167","author":"Akerman J.","key":"e_1_2_1_1_1"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/20.950889"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997876"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1088\/0953-8984\/19\/16\/165209"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391610"},{"key":"e_1_2_1_7_1","unstructured":"Freescale Document Number Brmramslscltrl. 2007. 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