{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,31]],"date-time":"2026-03-31T01:45:00Z","timestamp":1774921500430,"version":"3.50.1"},"reference-count":53,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2013,9,1]],"date-time":"2013-09-01T00:00:00Z","timestamp":1377993600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2013,9]]},"abstract":"<jats:p>\n            Reversible logic is gaining significance in the context of emerging technologies such as quantum computing since reversible circuits do not lose information during computation and there is one-to-one mapping between the inputs and outputs. In this work, we present a class of new designs for reversible binary and BCD adder circuits. The proposed designs are primarily optimized for the number of ancilla inputs and the number of garbage outputs and are designed for possible best values for the quantum cost and delay. In reversible circuits, in addition to the primary inputs, some constant input bits are used to realize different logic functions which are referred to as ancilla inputs and are overheads that need to be reduced. Further, the garbage outputs which do not contribute to any useful computations but are needed to maintain reversibility are also overheads that need to be reduced in reversible designs. First, we propose two new designs for the reversible ripple carry adder: (i) one with no input carry\n            <jats:italic>c<\/jats:italic>\n            <jats:sub>0<\/jats:sub>\n            and no ancilla input bits, and (ii) one with input carry\n            <jats:italic>c<\/jats:italic>\n            <jats:sub>0<\/jats:sub>\n            and no ancilla input bits. The proposed reversible ripple carry adder designs with no ancilla input bits have less quantum cost and logic depth (delay) compared to their existing counterparts in the literature. In these designs, the quantum cost and delay are reduced by deriving designs based on the reversible Peres gate and the TR gate. Next, four new designs for the reversible BCD adder are presented based on the following two approaches: (i) the addition is performed in binary mode and correction is applied to convert to BCD when required through detection and correction, and (ii) the addition is performed in binary mode and the result is always converted using a binary to BCD converter. The proposed reversible binary and BCD adders can be applied in a wide variety of digital signal processing applications and constitute important design components of reversible computing.\n          <\/jats:p>","DOI":"10.1145\/2491682","type":"journal-article","created":{"date-parts":[[2013,10,3]],"date-time":"2013-10-03T13:37:30Z","timestamp":1380807450000},"page":"1-31","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":73,"title":["Design of efficient reversible logic-based binary and BCD adder circuits"],"prefix":"10.1145","volume":"9","author":[{"given":"Himanshu","family":"Thapliyal","sequence":"first","affiliation":[{"name":"University of South Florida, Tampa, FL"}]},{"given":"Nagarajan","family":"Ranganathan","sequence":"additional","affiliation":[{"name":"University of South Florida, Tampa, FL"}]}],"member":"320","published-online":{"date-parts":[[2013,10,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2005.05.005"},{"key":"e_1_2_1_2_1","doi-asserted-by":"crossref","unstructured":"Bayrakci A. and Akkas A. 2007. Reduced delay bcd adder. http:\/\/www.csie.ncue.edu.tw\/csie\/ic\/Seminar_new\/9701\/971020\/971020_02.pdf.  Bayrakci A. and Akkas A. 2007. Reduced delay bcd adder. http:\/\/www.csie.ncue.edu.tw\/csie\/ic\/Seminar_new\/9701\/971020\/971020_02.pdf.","DOI":"10.1109\/ASAP.2007.4429991"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2008.04.003"},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the IEEE Symposium on VLSI. 83--88","author":"Bruce J. W."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2035451"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1324177.1324181"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/786450.786615"},{"key":"e_1_2_1_8_1","unstructured":"Cowlishaw M. 2010. Decimal arithmetic faq part 3 hardware questions. http:\/\/speleotrove.com\/decimal\/decifaq3.html.  Cowlishaw M. 2010. Decimal arithmetic faq part 3 hardware questions. http:\/\/speleotrove.com\/decimal\/decifaq3.html."},{"key":"e_1_2_1_9_1","unstructured":"Cuccaro S. A. Draper T. G. Kutin S. A. and Moulton D. P. 2004. A new quantum ripple-carry addition circuit. http:\/\/arXiv.org\/quant-ph\/0410184.  Cuccaro S. A. Draper T. G. Kutin S. A. and Moulton D. P. 2004. A new quantum ripple-carry addition circuit. http:\/\/arXiv.org\/quant-ph\/0410184."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9260(02)00051-2"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2005.9"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01857727"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2017215"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2008.42"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.871622"},{"key":"e_1_2_1_16_1","first-page":"974","article-title":"Design of a novel reversible multiplier circuit using hng gate in nanotechnology","volume":"3","author":"Haghparast M.","year":"2008","journal-title":"World Appl. Sci. J."},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems. 437--441","author":"Hari S. K. S."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.858352"},{"key":"e_1_2_1_19_1","doi-asserted-by":"crossref","unstructured":"James R. K. Jacob K. P. and \n      Sasi S\n  . \n  2008\n  . Reversible binary coded decimal adders using toffoli gates. In Advances in Computational Algorithms and Data Analysis Lecture Notes in Electrical Engineering vol. \n  14 Springer 117--131.  James R. K. Jacob K. P. and Sasi S. 2008. Reversible binary coded decimal adders using toffoli gates. In Advances in Computational Algorithms and Data Analysis Lecture Notes in Electrical Engineering vol. 14 Springer 117--131.","DOI":"10.1007\/978-1-4020-8919-0_9"},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the International Conference on Computer and Information Technology. 515--519","author":"Khan M.","year":"2002"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2007.01.007"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-007-5042-2"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-008-5078-y"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.836735"},{"key":"e_1_2_1_25_1","unstructured":"Maslov D. and Miller D. M. 2006. Comparison of the cost metrics for reversible and quantum logic synthesis. http:\/\/arxiv.org\/abs\/quant-ph\/0511008.  Maslov D. and Miller D. M. 2006. Comparison of the cost metrics for reversible and quantum logic synthesis. http:\/\/arxiv.org\/abs\/quant-ph\/0511008."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1324177.1324179"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11128-009-0106-0"},{"key":"e_1_2_1_28_1","first-page":"787","article-title":"Design and optimization of reversible bcd adder\/subtractor circuit for quantum and nanotechnology based systems","volume":"4","author":"Mohammadi M.","year":"2008","journal-title":"World Appl. Sci. J."},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1142\/S0219749909005523"},{"key":"e_1_2_1_30_1","unstructured":"Nielsen M. A. and Chuang I. L. 2000. Quantum Computation and Quantum Information. Cambridge University Press London UK.   Nielsen M. A. and Chuang I. L. 2000. Quantum Computation and Quantum Information. Cambridge University Press London UK."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2006.355056"},{"key":"e_1_2_1_32_1","volume-title":"Computer Arithmetic: Algorithms and Hardware Designs","author":"Parhami B.","year":"2010","edition":"2"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.32.3266"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1216396.1216399"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/bxm116"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811448"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.53.2855"},{"key":"e_1_2_1_38_1","first-page":"276","article-title":"Quantum arithmetic circuits: A survey. IEICE","volume":"5","author":"Takahashi Y.","year":"2010","journal-title":"Trans. Fundam. E92-A"},{"key":"e_1_2_1_39_1","first-page":"6","article-title":"A linear-size quantum circuit for addition with no ancillary qubits","volume":"5","author":"Takahashi Y.","year":"2005","journal-title":"Quantum Inf. Comput."},{"key":"e_1_2_1_40_1","unstructured":"Takahashi Y. Tani S. and Kunihiro N. 2009. Quantum addition circuits and unbounded fan-out. http:\/\/arxiv.org\/abs\/0910.2530.   Takahashi Y. Tani S. and Kunihiro N. 2009. Quantum addition circuits and unbounded fan-out. http:\/\/arxiv.org\/abs\/0910.2530."},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.optlastec.2009.06.017"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2009.49"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/1877745.1877748"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2009.2025038"},{"key":"e_1_2_1_45_1","volume-title":"Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'11)","author":"Thapliyal H."},{"key":"e_1_2_1_46_1","volume-title":"Proceedings of the 10th IEEE International Conference on Nanotechnology. 1113--1116","author":"Thapliyal H."},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2007.12.006"},{"key":"e_1_2_1_48_1","doi-asserted-by":"crossref","unstructured":"Toffoli T. 1980. Reversible computing. Tech. memo MIT\/LCS\/TM-151 MIT Lab for Computer Science.  Toffoli T. 1980. Reversible computing. Tech. memo MIT\/LCS\/TM-151 MIT Lab for Computer Science.","DOI":"10.21236\/ADA082021"},{"key":"e_1_2_1_49_1","unstructured":"Trisetyarso A. and Van Meter R. 2009. Circuit design for a measurement-based quantum carry-lookahead adder. http:\/\/arxiv.org\/abs\/0903.0748.  Trisetyarso A. and Van Meter R. 2009. Circuit design for a measurement-based quantum carry-lookahead adder. http:\/\/arxiv.org\/abs\/0903.0748."},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.54.147"},{"key":"e_1_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2010.2040930"},{"key":"e_1_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837439"},{"key":"e_1_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/bxm042"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2491682","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2491682","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:39:22Z","timestamp":1750235962000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2491682"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":53,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2013,9]]}},"alternative-id":["10.1145\/2491682"],"URL":"https:\/\/doi.org\/10.1145\/2491682","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"value":"1550-4832","type":"print"},{"value":"1550-4840","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,9]]},"assertion":[{"value":"2010-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-10-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}