{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T15:38:00Z","timestamp":1781797080712,"version":"3.54.5"},"reference-count":25,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2014,1,1]],"date-time":"2014-01-01T00:00:00Z","timestamp":1388534400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF-1018216, CCF-1018750"],"award-info":[{"award-number":["CCF-1018216, CCF-1018750"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100004316","name":"International Business Machines Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004316","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["Commun. ACM"],"published-print":{"date-parts":[[2014,1]]},"abstract":"<jats:p>Three-dimensional integrated circuit (3D IC) with through-silicon-via (TSV) is believed to offer new levels of efficiency, power, performance, and form-factor advantages over the conventional 2D IC. However, 3D IC involves disruptive manufacturing technologies compared to conventional 2D IC. TSVs cause significant thermomechanical stress that may seriously affect performance, leakage, and reliability of circuits. In this paper, we discuss an efficient and accurate full-chip thermomechanical stress and reliability analysis tool as well as a design optimization methodology to alleviate mechanical reliability issues in 3D ICs. First, we analyze detailed thermomechanical stress induced by TSVs in conjunction with various associated structures such as landing pad and dielectric liner. Then, we explore and validate the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed finite element analysis (FEA) simulations. Next, we apply this linear superposition method to full-chip stress simulation and a reliability metric named the von Mises yield criterion. Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs.<\/jats:p>","DOI":"10.1145\/2494536","type":"journal-article","created":{"date-parts":[[2014,1,2]],"date-time":"2014-01-02T13:09:43Z","timestamp":1388668183000},"page":"107-115","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":60,"title":["TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC"],"prefix":"10.1145","volume":"57","author":[{"given":"Moongon","family":"Jung","sequence":"first","affiliation":[{"name":"Georgia Institute of Technology GA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Joydeep","family":"Mitra","sequence":"additional","affiliation":[{"name":"University of Texas at Austin TX"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"David Z.","family":"Pan","sequence":"additional","affiliation":[{"name":"University of Texas at Austin TX"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sung Kyu","family":"Lim","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology GA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2014,1]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of IEEE International Conference on Computer-Aided Design","author":"Athikulwongse K.","year":"2010","unstructured":"Athikulwongse , K. , Chakraborty , A. , Yang , J.S. , Pan , D.Z. , Lim , S.K. Stress -driven 3D-IC placement with TSV keep-out zone and regularity study . In Proceedings of IEEE International Conference on Computer-Aided Design ( 2010 ). Athikulwongse, K., Chakraborty, A., Yang, J.S., Pan, D.Z., Lim, S.K. Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. In Proceedings of IEEE International Conference on Computer-Aided Design (2010)."},{"key":"e_1_2_1_2_1","volume-title":"Impact of mechanical stress on the full chip timing for TSV-based 3D ICs","author":"Athikulwongse K.","year":"2013","unstructured":"Athikulwongse , K. , Yang , J.S. , Pan , D.Z. , Lim , S.K. Impact of mechanical stress on the full chip timing for TSV-based 3D ICs . IEEE Trans. Comput.-Aided Design Integr. Circuits Syst . ( 2013 ). Athikulwongse, K., Yang, J.S., Pan, D.Z., Lim, S.K. Impact of mechanical stress on the full chip timing for TSV-based 3D ICs. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. (2013)."},{"key":"e_1_2_1_3_1","volume-title":"IEEE International Solid-State Circuits Conference Digest Technical Papers","author":"der Plas G.V.","year":"2010","unstructured":"der Plas , G.V. et al. Design issues and considerations for low-cost 3D TSV IC technology . In IEEE International Solid-State Circuits Conference Digest Technical Papers ( 2010 ). der Plas, G.V. et al. Design issues and considerations for low-cost 3D TSV IC technology. In IEEE International Solid-State Circuits Conference Digest Technical Papers (2010)."},{"key":"e_1_2_1_4_1","first-page":"48","author":"Fick D.","year":"2013","unstructured":"Fick , D. , Dreslinski , R. , Giridhar , B. , Kim , G. , Seo , S. , Fojtik , M. , Satpathy , S. , Lee , Y. , Kim , D. , Liu , N. , Wieckowski , M. , Chen , G. , Mudge , T. , Blaauw , D. , Sylvester , S. Centip 3De: A cluster-based NTC architecture with 64 ARM Cortex -M3 cores in 3D stacked 130 nm CMOS. IEEE J. Solid-State Circuits 48 ( 2013 ). Fick, D., Dreslinski, R., Giridhar, B., Kim, G., Seo, S., Fojtik, M., Satpathy, S., Lee, Y., Kim, D., Liu, N., Wieckowski, M., Chen, G., Mudge, T., Blaauw, D., Sylvester, S. Centip3De: A cluster-based NTC architecture with 64 ARM Cortex-M3 cores in 3D stacked 130 nm CMOS. IEEE J. Solid-State Circuits 48 (2013).","journal-title":"CMOS. IEEE J. Solid-State Circuits"},{"key":"e_1_2_1_5_1","volume-title":"Introduction to Microfabrication","author":"Franssila S.","year":"2004","unstructured":"Franssila , S. Introduction to Microfabrication , John Wiley and Sons , 2004 . Franssila, S. Introduction to Microfabrication, John Wiley and Sons, 2004."},{"key":"e_1_2_1_6_1","unstructured":"FreePDK45. http:\/\/www.eda.ncsu.edu\/wiki\/FreePDK.  FreePDK45. http:\/\/www.eda.ncsu.edu\/wiki\/FreePDK."},{"key":"e_1_2_1_7_1","unstructured":"International Technology Roadmap for Semiconductors (2012 Update). http:\/\/www.itrs.net.  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Kim, D.H., Athikulwongse, K., Healy, M.B., Hossain, M.M., Jung, M., Khorosh, I., Kumar, G., Lee, Y.J., Lewis, D.L., Lin, T.W., Liu, C., Panth, S., Pathak, M., Ren, M., Shen, G., Song, T., Woo, D.H., Zhao, X., Kim, J., Choi, H., Loh, G.H., Lee, H.H.S., Lim, S.K. 3D-MAPS: 3D massively parallel processor with stacked memory. In IEEE International Solid-State Circuits Conference Digest of Technical Papers (2012)."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687524"},{"key":"e_1_2_1_14_1","volume-title":"IEEE Electronic Components and Technology Conference","author":"Liu X.","year":"2009","unstructured":"Liu , X. , Chen , Q. , Dixit , P. , Chatterjee , R. , Tummala , R.R. , Sitaraman , S.K. Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV) . In IEEE Electronic Components and Technology Conference ( 2009 ). Liu, X., Chen, Q., Dixit, P., Chatterjee, R., Tummala, R.R., Sitaraman, S.K. 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In IEEE Electronic Components and Technology Conference ( 2009 ). Lu, K.H., Zhang, X., Ryu, S.K., Im, J., Huang, R., Ho, P.S. Thermomechanical reliability of 3-D ICs containing through silicon vias. In IEEE Electronic Components and Technology Conference (2009)."},{"key":"e_1_2_1_17_1","first-page":"32","author":"Ong J.M.G.","year":"2009","unstructured":"Ong , J.M.G. , Tay , A.A.O. , Zhang , X. , Kripesh , V. , Lim , Y.K. , Yeo , D. , Chen , K.C. , Tan , J.B. , Hsia , L.C. , Sohn , D.K. Optimization of the thermomechanical reliability of a 65 nm Cu\/low-k large-die flip chip package. IEEE Trans. Compon. Packag. Tech. 32 ( 2009 ). Ong, J.M.G., Tay, A.A.O., Zhang, X., Kripesh, V., Lim, Y.K., Yeo, D., Chen, K.C., Tan, J.B., Hsia, L.C., Sohn, D.K. Optimization of the thermomechanical reliability of a 65 nm Cu\/low-k large-die flip chip package. IEEE Trans. Compon. Packag. Tech. 32 (2009).","journal-title":"IEEE Trans. Compon. Packag. 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