{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,30]],"date-time":"2025-10-30T22:27:06Z","timestamp":1761863226376,"version":"3.41.0"},"reference-count":115,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2013,8,1]],"date-time":"2013-08-01T00:00:00Z","timestamp":1375315200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001665","name":"Agence Nationale de la Recherche","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001665","id-type":"DOI","asserted-by":"publisher"}]},{"name":"French General Armaments Directorate"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Comput. Surv."],"published-print":{"date-parts":[[2013,8]]},"abstract":"<jats:p>Throughput, flexibility, and security form the design trilogy of reconfigurable crypto engines; they must be carefully considered without reducing the major role of classical design constraints, such as surface, power consumption, dependability, and cost. Applications such as network security, Virtual Private Networks (VPN), Digital Rights Management (DRM), and pay per view have drawn attention to these three constraints. For more than ten years, many studies in the field of cryptographic engineering have focused on the design of optimized high-throughput hardware cryptographic cores (e.g., symmetric and asymmetric key block ciphers, stream ciphers, and hash functions). The flexibility of cryptographic systems plays a very important role in their practical application. Reconfigurable hardware systems can evolve with algorithms, face up to new types of attacks, and guarantee interoperability between countries and institutions. The flexibility of reconfigurable crypto processors and crypto coprocessors has reached new levels with the emergence of dynamically reconfigurable hardware architectures and tools. Last but not least, the security of systems that handle confidential information needs to be thoroughly evaluated at the design stage in order to meet security objectives that depend on the importance of the information to be protected and on the cost of protection. Usually, designers tackle security problems at the same time as other design constraints and in many cases target only one security objective, for example, a side-channel attack countermeasures, fault tolerance capability, or the monitoring of the device environment. Only a few authors have addressed all three design constraints at the same time. In particular, key management security (e.g., secure key generation and transmission, the use of a hierarchical key structure composed of session keys and master keys) has frequently been neglected to the benefit of performance and\/or flexibility. Nevertheless, a few authors propose original processor architectures based on multi-crypto-processor structures and reconfigurable cryptographic arrays. In this article, we review published works on symmetric key crypto engines and present current trends and design challenges.<\/jats:p>","DOI":"10.1145\/2501654.2501655","type":"journal-article","created":{"date-parts":[[2013,8,27]],"date-time":"2013-08-27T12:58:51Z","timestamp":1377608331000},"page":"1-32","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":56,"title":["Architectures of flexible symmetric key crypto engines\u2014a survey"],"prefix":"10.1145","volume":"45","author":[{"given":"Lilian","family":"Bossuet","sequence":"first","affiliation":[{"name":"University of Lyon, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Grand","sequence":"additional","affiliation":[{"name":"University of Bordeaux, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lubos","family":"Gaspar","sequence":"additional","affiliation":[{"name":"University of Lyon, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Viktor","family":"Fischer","sequence":"additional","affiliation":[{"name":"University of Lyon, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guy","family":"Gogniat","sequence":"additional","affiliation":[{"name":"University of South Brittany, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,8,30]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Altera 2011. Cyclone III fpga: Security. http:\/\/www.altera.com\/products\/devices\/cyclone3\/overview\/security\/cy3-security.html.  Altera 2011. Cyclone III fpga: Security. http:\/\/www.altera.com\/products\/devices\/cyclone3\/overview\/security\/cy3-security.html."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147040"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2005.862423"},{"volume-title":"Security Engineering. A Guide to Building Dependable Distributed Systems","author":"Anderson R.","key":"e_1_2_1_4_1","unstructured":"Anderson , R. 2001. Security Engineering. A Guide to Building Dependable Distributed Systems . Wiley . Anderson, R. 2001. Security Engineering. A Guide to Building Dependable Distributed Systems. Wiley."},{"key":"e_1_2_1_5_1","doi-asserted-by":"crossref","unstructured":"Badrignans B. Danger J.-L. Fischer V. and Gogniat G. 2011. Security Trends for FPGAS: From Secured to Secure Reconfigurable Systems. Springer.   Badrignans B. Danger J.-L. Fischer V. and Gogniat G. 2011. Security Trends for FPGAS: From Secured to Secure Reconfigurable Systems. Springer.","DOI":"10.1007\/978-94-007-1338-3"},{"volume-title":"Proceedings of the 2nd International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE'11)","author":"Bangerter E.","key":"e_1_2_1_6_1","unstructured":"Bangerter , E. , Gullash , D. , and Krenn , S . 2011. Cache games-bringing access-based cache attacks on AES to practice . In Proceedings of the 2nd International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE'11) . 215--221. Bangerter, E., Gullash, D., and Krenn, S. 2011. Cache games-bringing access-based cache attacks on AES to practice. In Proceedings of the 2nd International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE'11). 215--221."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-010-9084-8"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.24"},{"key":"e_1_2_1_9_1","unstructured":"Bernstein D. 2005. Cache-timing attacks on aes. Res. rep. http:\/\/cr.yp.to\/antiforgery\/cachetiming-20050414.pdf.  Bernstein D. 2005. Cache-timing attacks on aes. Res. rep. http:\/\/cr.yp.to\/antiforgery\/cachetiming-20050414.pdf."},{"key":"e_1_2_1_10_1","doi-asserted-by":"crossref","unstructured":"Bernstein D. J. Buchmann J. and Dahmen E. 2008. Post-Quantum Cryptography. Springer.   Bernstein D. J. Buchmann J. and Dahmen E. 2008. Post-Quantum Cryptography. Springer.","DOI":"10.1007\/978-3-540-88702-7"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/1987535.1987586"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.862745"},{"volume-title":"Communicating Embedded Systems for Networks","author":"Bossuet L.","key":"e_1_2_1_13_1","unstructured":"Bossuet , L. and Gogniat , G . Hardware security in embedded systems . In Communicating Embedded Systems for Networks , F. Krief, Ed., Wiley-ISTE. Bossuet, L. and Gogniat, G. Hardware security in embedded systems. In Communicating Embedded Systems for Networks, F. Krief, Ed., Wiley-ISTE."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1155\/2007\/23496"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1504\/IJES.2006.010166"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.233"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-24714-2_15"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379238"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2006.02.001"},{"key":"e_1_2_1_20_1","volume-title":"S. M., Hoffman, G., Meziani, M.","author":"Cayrel P. L.","year":"2011","unstructured":"Cayrel , P. L. , El Yousi Alaoui , S. M., Hoffman, G., Meziani, M. , and Niebuhr, R. 2011 . Recent progress in code-based cryptography. In Proceedings of the International Conference on Information Security and Assurance (ISA'11). Springer , 21--32. Cayrel, P. L., El Yousi Alaoui, S. M., Hoffman, G., Meziani, M., and Niebuhr, R. 2011. Recent progress in code-based cryptography. In Proceedings of the International Conference on Information Security and Assurance (ISA'11). Springer, 21--32."},{"volume-title":"Proceedings of the Workshop on Circuits, Systems and Signal Processing (ProRisc'06)","author":"Chaves R.","key":"e_1_2_1_21_1","unstructured":"Chaves , R. , Kuzmanov , G. , Vassiliadis , S. , and Sousa , L. A . 2006. Reconfigurable cryptographic processor . In Proceedings of the Workshop on Circuits, Systems and Signal Processing (ProRisc'06) . Chaves, R., Kuzmanov, G., Vassiliadis, S., and Sousa, L. A. 2006. Reconfigurable cryptographic processor. In Proceedings of the Workshop on Circuits, Systems and Signal Processing (ProRisc'06)."},{"volume-title":"Proceedings of the 20th USENIX Conference on Security. 6.","author":"Checkoway S.","key":"e_1_2_1_22_1","unstructured":"Checkoway , S. , McCoy , D. , Kantor , B. , Anderson , D. , Shacham , H. , Savage , S. , Koscher , K. , Czeskis , A. , Roesner , F. , and Kohno , T . 2011. Comprehensive experimental analyses of automotive attack surfaces . In Proceedings of the 20th USENIX Conference on Security. 6. Checkoway, S., McCoy, D., Kantor, B., Anderson, D., Shacham, H., Savage, S., Koscher, K., Czeskis, A., Roesner, F., and Kohno, T. 2011. Comprehensive experimental analyses of automotive attack surfaces. In Proceedings of the 20th USENIX Conference on Security. 6."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1086297.1086308"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30574-3_23"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.158"},{"key":"e_1_2_1_26_1","unstructured":"Davies P. 2003. Flexible Security. White Paper Cryptography and Interoperability. Thales.  Davies P. 2003. Flexible Security. White Paper Cryptography and Interoperability. Thales."},{"key":"e_1_2_1_27_1","volume-title":"Proceedings of 2nd International Conference on Computer Engineering and Technology (ICCET'10)","volume":"6","author":"Deguang L.","unstructured":"Deguang , L. , Jinyi , C. , Xingd , G. , Ankang , Z. , and Conglan , L . 2010. Parallel aes algorithm for fast data encryption on gpu . In Proceedings of 2nd International Conference on Computer Engineering and Technology (ICCET'10) . Vol. 6 . ASME, New York, 1--6. Deguang, L., Jinyi, C., Xingd, G., Ankang, Z., and Conglan, L. 2010. Parallel aes algorithm for fast data encryption on gpu. In Proceedings of 2nd International Conference on Computer Engineering and Technology (ICCET'10). Vol. 6. ASME, New York, 1--6."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACSAC.2006.21"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11416-007-0062-0"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2007.30"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1314354.1314360"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2006.1649595"},{"volume-title":"Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS'03)","author":"Elbirt A. J.","key":"e_1_2_1_33_1","unstructured":"Elbirt , A. J. and Paar , C . 2003. Instruction-level distributed processing for symmetric-key cryptography . In Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS'03) . IEEE Computer Society, Los Alamitos, CA, 78--88. Elbirt, A. J. and Paar, C. 2003. Instruction-level distributed processing for symmetric-key cryptography. In Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS'03). IEEE Computer Society, Los Alamitos, CA, 78--88."},{"volume-title":"Proceedings of the International Symposium on Hardware Oriented Security and Trust (HOST'11)","author":"Feller T.","key":"e_1_2_1_34_1","unstructured":"Feller , T. , Malipatlolla , S. , Meister , D. , and Huss , S. A . 2011. TyniTPM: A lightweight module aimed to ip protection and trusted embedded platforms . In Proceedings of the International Symposium on Hardware Oriented Security and Trust (HOST'11) . 60--74. Feller, T., Malipatlolla, S., Meister, D., and Huss, S. A. 2011. TyniTPM: A lightweight module aimed to ip protection and trusted embedded platforms. In Proceedings of the International Symposium on Hardware Oriented Security and Trust (HOST'11). 60--74."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2008.76"},{"volume-title":"Proceedings of the 3rd Norsk Information Security Conference (NISK'10)","author":"Gaber C.","key":"e_1_2_1_36_1","unstructured":"Gaber , C. and Pailles , J. C . 2010. Security and trust for mobile phones based on virtualization . In Proceedings of the 3rd Norsk Information Security Conference (NISK'10) . 93--103. Gaber, C. and Pailles, J. C. 2010. Security and trust for mobile phones based on virtualization. In Proceedings of the 3rd Norsk Information Security Conference (NISK'10). 93--103."},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.86"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1155\/ES\/2006\/56320"},{"volume-title":"Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC'11)","author":"Gaspar L.","key":"e_1_2_1_39_1","unstructured":"Gaspar , L. , Fischer , V. , Bossuet , L. , and Fouquet , R . 2011. Secure extensions of soft core general-purpose processors for symmetric key cryptography . In Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC'11) . IEEE CAS Society. Gaspar, L., Fischer, V., Bossuet, L., and Fouquet, R. 2011. Secure extensions of soft core general-purpose processors for symmetric key cryptography. In Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC'11). IEEE CAS Society."},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2010.38"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/586110.586132"},{"volume-title":"Proceedings of the 30th Annual International Conference on Theory and Applications of Cryptographic Techniques: Advanced in Cryptology (EUROCRYPT'11)","author":"Gentry G.","key":"e_1_2_1_42_1","unstructured":"Gentry , G. and Halevi , S . 2011. Implementing grentry's fully-homomorphic encryption scheme . In Proceedings of the 30th Annual International Conference on Theory and Applications of Cryptographic Techniques: Advanced in Cryptology (EUROCRYPT'11) . K. G. Paterson, Ed., Springer, 129--148. Gentry, G. and Halevi, S. 2011. Implementing grentry's fully-homomorphic encryption scheme. In Proceedings of the 30th Annual International Conference on Theory and Applications of Cryptographic Techniques: Advanced in Cryptology (EUROCRYPT'11). K. G. Paterson, Ed., Springer, 129--148."},{"volume-title":"Intel Mobility group","author":"Gueron S.","key":"e_1_2_1_43_1","unstructured":"Gueron , S. 2010. Intel Advanced Encryption Standard (AES) Instructions Set. White paper , Intel Mobility group , Israel Development Center , Israel . Gueron, S. 2010. Intel Advanced Encryption Standard (AES) Instructions Set. White paper, Intel Mobility group, Israel Development Center, Israel."},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403505"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.912030"},{"volume-title":"Proceedings of the IEEE Military Communication Conference (MILCOM'09)","author":"Grand M.","key":"e_1_2_1_46_1","unstructured":"Grand , M. , Bossuet , L. , Le Gal , B. , Dallet , D. , and Gogniat , G . 2009. A reconfigurable crypto sub system for the software communication architecture . In Proceedings of the IEEE Military Communication Conference (MILCOM'09) . IEEE Press, 2708--2714. Grand, M., Bossuet, L., Le Gal, B., Dallet, D., and Gogniat, G. 2009. A reconfigurable crypto sub system for the software communication architecture. In Proceedings of the IEEE Military Communication Conference (MILCOM'09). IEEE Press, 2708--2714."},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.5555\/1987535.1987542"},{"volume-title":"Proceedings of the International Conference on Field-Programmable Technology (FPT'07)","author":"Guneysu T.","key":"e_1_2_1_48_1","unstructured":"Guneysu , T. , Moller , B. , and Paar , C . 2007. Dynamic intellectual property protection for reconfigurable devices . In Proceedings of the International Conference on Field-Programmable Technology (FPT'07) . IEEE Electron Devices Society, 169--176. Guneysu, T., Moller, B., and Paar, C. 2007. Dynamic intellectual property protection for reconfigurable devices. In Proceedings of the International Conference on Field-Programmable Technology (FPT'07). IEEE Electron Devices Society, 169--176."},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/1506409.1506429"},{"key":"e_1_2_1_50_1","doi-asserted-by":"crossref","first-page":"443","DOI":"10.1007\/978-3-540-73625-7_45","article-title":"Review of hardware architectures for advanced encryption standard implementations considering wireless sensor networks. In Proceedings of the 7th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'07)","volume":"4599","author":"H\u00e4m\u00e4l\u00e4inen P.","year":"2007","unstructured":"H\u00e4m\u00e4l\u00e4inen , P. , H\u00e4nnik\u00e4inen , M. , and H\u00e4m\u00e4l\u00e4inen , T. 2007 . Review of hardware architectures for advanced encryption standard implementations considering wireless sensor networks. In Proceedings of the 7th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'07) . Lecture Notes in Computer Science , vol. 4599 , Spring er, 443 -- 453 . H\u00e4m\u00e4l\u00e4inen, P., H\u00e4nnik\u00e4inen, M., and H\u00e4m\u00e4l\u00e4inen, T. 2007. Review of hardware architectures for advanced encryption standard implementations considering wireless sensor networks. In Proceedings of the 7th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'07). Lecture Notes in Computer Science, vol. 4599, Springer, 443--453.","journal-title":"Lecture Notes in Computer Science"},{"volume-title":"Proceedings of the 9th IEEE NEWCAS Conference. 1--4.","author":"Hely D.","key":"e_1_2_1_51_1","unstructured":"Hely , D. , Rosenfeld , K. , and Karri , R . 2011. Security challenges during vlsi test . In Proceedings of the 9th IEEE NEWCAS Conference. 1--4. Hely, D., Rosenfeld, K., and Karri, R. 2011. Security challenges during vlsi test. In Proceedings of the 9th IEEE NEWCAS Conference. 1--4."},{"key":"e_1_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.11"},{"volume-title":"Proceedings of the 38th Asilomar Conference on Signals, Systems and Computers. 488--492","author":"Hodjat A.","key":"e_1_2_1_53_1","unstructured":"Hodjat , A. and Verbauwhede , I . 2004b. Interfacing a high speed crypto accelerator to an embedded CPU . In Proceedings of the 38th Asilomar Conference on Signals, Systems and Computers. 488--492 . Hodjat, A. and Verbauwhede, I. 2004b. Interfacing a high speed crypto accelerator to an embedded CPU. In Proceedings of the 38th Asilomar Conference on Signals, Systems and Computers. 488--492."},{"key":"e_1_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.49"},{"key":"e_1_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-89598-5_18"},{"volume-title":"Proceedings of the 5th Annual International Workshop on Selected Areas in Cryptography (SAC'98)","author":"Kaps J. P.","key":"e_1_2_1_56_1","unstructured":"Kaps , J. P. and Paar , C . 1998. Fast des implementation for fpgas and its application to a universal key-search machine . In Proceedings of the 5th Annual International Workshop on Selected Areas in Cryptography (SAC'98) . S. E. Tavares and H. Meijer, Eds., Springer, 234--247. Kaps, J. P. and Paar, C. 1998. Fast des implementation for fpgas and its application to a universal key-search machine. In Proceedings of the 5th Annual International Workshop on Selected Areas in Cryptography (SAC'98). S. E. Tavares and H. Meijer, Eds., Springer, 234--247."},{"key":"e_1_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2010.299"},{"key":"e_1_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2004.52"},{"key":"e_1_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2010.34"},{"volume-title":"Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04)","author":"Kuzmanov G.","key":"e_1_2_1_60_1","unstructured":"Kuzmanov , G. , Gaydajiev , G. N. , and Vassiliadis , S . 2004. The molen processor prototype . In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04) . 296--299. Kuzmanov, G., Gaydajiev, G. N., and Vassiliadis, S. 2004. The molen processor prototype. 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Masters thesis, University of Central Florida."},{"key":"e_1_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICSPC.2007.4728256"},{"volume-title":"Proceedings of the Software Design Radio Technical Conference (SDRForum'08)","author":"Martin A.","key":"e_1_2_1_66_1","unstructured":"Martin , A. , Newman , T. , and Morotake , D . 2008. Development approaches for an international tactical radio cryptographic api . In Proceedings of the Software Design Radio Technical Conference (SDRForum'08) . 1--6. Martin, A., Newman, T., and Morotake, D. 2008. Development approaches for an international tactical radio cryptographic api. In Proceedings of the Software Design Radio Technical Conference (SDRForum'08). 1--6."},{"key":"e_1_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2009.5224964"},{"volume-title":"Proceeding of 7th Southern International Conference on Programmable Logic (SPL'11)","author":"Malipatlolla S.","key":"e_1_2_1_68_1","unstructured":"Malipatlolla , S. and Huss , S. A . 2011. A novel method for secure intellectual property deployment in embedded systems . In Proceeding of 7th Southern International Conference on Programmable Logic (SPL'11) . IEEE Circuits and Systems Society, 1--6. Malipatlolla, S. and Huss, S. A. 2011. A novel method for secure intellectual property deployment in embedded systems. In Proceeding of 7th Southern International Conference on Programmable Logic (SPL'11). IEEE Circuits and Systems Society, 1--6."},{"key":"e_1_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.5555\/648252.752394"},{"key":"e_1_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1145\/2046707.2046722"},{"key":"e_1_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-27954-6_1"},{"volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe (DATE'07)","author":"Mucci C.","key":"e_1_2_1_72_1","unstructured":"Mucci , C. , Vanzolini , L. , Campi , F. , and Toma , M . 2007. Interactive presentation: Implementation of aes\/rijndael on a dynamically reconfigurable architecture . In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'07) . ACM Press, New York, 355--360. Mucci, C., Vanzolini, L., Campi, F., and Toma, M. 2007. Interactive presentation: Implementation of aes\/rijndael on a dynamically reconfigurable architecture. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'07). ACM Press, New York, 355--360."},{"key":"e_1_2_1_73_1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2005.42"},{"key":"e_1_2_1_74_1","doi-asserted-by":"publisher","DOI":"10.1145\/2046660.2046682"},{"key":"e_1_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78610-8_37"},{"key":"e_1_2_1_76_1","doi-asserted-by":"publisher","DOI":"10.1145\/501983.502000"},{"key":"e_1_2_1_77_1","doi-asserted-by":"publisher","DOI":"10.1007\/11605805_1"},{"volume-title":"Proceedings of 8th International Meeting High Performance Computing for Computational Science (VECPAR'08)","author":"Peric\u00e0s M.","key":"e_1_2_1_78_1","unstructured":"Peric\u00e0s , M. , Chaves , R. , Gaydadjiev , G. N. , Vassiliadis , S. , and Valero , M . 2008. vectorized aes core for high-throughput secure environments . In Proceedings of 8th International Meeting High Performance Computing for Computational Science (VECPAR'08) . 83--94. Peric\u00e0s, M., Chaves, R., Gaydadjiev, G. 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In Proceedings of 8th International Meeting High Performance Computing for Computational Science (VECPAR'08). 83--94."},{"key":"e_1_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.200"},{"key":"e_1_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1145\/1015047.1015049"},{"key":"e_1_2_1_81_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.514113"},{"key":"e_1_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-10628-6_7"},{"key":"e_1_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.5555\/1964621.1964631"},{"key":"e_1_2_1_84_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2008.53"},{"key":"e_1_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-85893-5_7"},{"key":"e_1_2_1_86_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11036-007-0024-2"},{"key":"e_1_2_1_87_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2007.05.005"},{"key":"e_1_2_1_88_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1193231"},{"key":"e_1_2_1_89_1","volume-title":"Proceedings of the Non-Invasive Attacks Testing Workshop (NIAT'11)","author":"Standaert F.-X.","year":"2011","unstructured":"Standaert , F.-X. 2011 . Some hints on the evaluation metrics and tools for side-channel attacks . In Proceedings of the Non-Invasive Attacks Testing Workshop (NIAT'11) . http:\/\/perso.uclouvain.be\/fstandae\/PUBLIS\/107_slides.pdf. Standaert, F.-X. 2011. Some hints on the evaluation metrics and tools for side-channel attacks. In Proceedings of the Non-Invasive Attacks Testing Workshop (NIAT'11). http:\/\/perso.uclouvain.be\/fstandae\/PUBLIS\/107_slides.pdf."},{"key":"e_1_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45234-8_68"},{"key":"e_1_2_1_91_1","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120870"},{"key":"e_1_2_1_92_1","volume-title":"AEGIS: Architecture for tamper-evident and tamper-resistant processing. MIT, Memo-461.","author":"Suh G. E.","year":"2003","unstructured":"Suh , G. E. , Clarke , D. , Gassend , B. , van Dijk , M. , and Devadas , S . 2003 . AEGIS: Architecture for tamper-evident and tamper-resistant processing. MIT, Memo-461. Suh, G. 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Low latency solution for confidentiality and integrity checking in embedded systems with off-chip memory . In Proceedings of the Workshop on Reconfigurable Communication-centric SoCs (ReCoSoc'07) .146--153. Vaslin, R., Gogniat G., Diguet, J. P., Wandeley, E., Tessier, R., and Burleson, W. 2007. Low latency solution for confidentiality and integrity checking in embedded systems with off-chip memory. In Proceedings of the Workshop on Reconfigurable Communication-centric SoCs (ReCoSoc'07).146--153."},{"volume-title":"Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'10)","author":"Valtchanov B.","key":"e_1_2_1_104_1","unstructured":"Valtchanov , B. , Fischer , V. , Aubert , A. , and Bernard , F . 2010. Characterization of randomness sources in ring oscillator-based true random number generators in fpgas . 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Advance product specification ds180. http:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds180_7Series_Overview.pdf.  Xilinx Corp. 2012. Virtex 7 series FPGAs overview. Advance product specification ds180. http:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds180_7Series_Overview.pdf."},{"key":"e_1_2_1_115_1","doi-asserted-by":"publisher","DOI":"10.1145\/1023833.1023873"}],"container-title":["ACM Computing Surveys"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2501654.2501655","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2501654.2501655","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:28:48Z","timestamp":1750231728000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2501654.2501655"}},"subtitle":["From hardware coprocessor to multi-crypto-processor system on chip"],"short-title":[],"issued":{"date-parts":[[2013,8]]},"references-count":115,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2013,8]]}},"alternative-id":["10.1145\/2501654.2501655"],"URL":"https:\/\/doi.org\/10.1145\/2501654.2501655","relation":{},"ISSN":["0360-0300","1557-7341"],"issn-type":[{"type":"print","value":"0360-0300"},{"type":"electronic","value":"1557-7341"}],"subject":[],"published":{"date-parts":[[2013,8]]},"assertion":[{"value":"2011-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-06-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-08-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}