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Archit. Code Optim."],"published-print":{"date-parts":[[2013,9,16]]},"abstract":"<jats:p>\n            As the number of cores and threads in throughput accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network design. This article explores throughput-effective Network-on-Chips (NoC) for future compute accelerators that employ Bulk-Synchronous Parallel (BSP) programming models such as CUDA and OpenCL. A hardware optimization is \u201cthroughput effective\u201d if it improves parallel application-level performance per unit chip area. We evaluate performance of future looking workloads using detailed closed-loop simulations modeling compute nodes, NoC, and the DRAM memory system. We start from a mesh design with bisection bandwidth balanced to off-chip demand. Accelerator workloads tend to demand high off-chip memory bandwidth which results in a many-to-few traffic pattern when coupled with expected technology constraints of slow growth in pins-per-chip. Leveraging these observations we reduce NoC area by proposing a \u201ccheckerboard\u201d NoC which alternates between conventional\n            <jats:italic>full<\/jats:italic>\n            routers and\n            <jats:italic>half<\/jats:italic>\n            routers with limited connectivity. Next, we show that increasing network terminal bandwidth at the nodes connected to DRAM controllers alleviates a significant fraction of the remaining imbalance resulting from the many-to-few traffic pattern. Furthermore, we propose a \u201cdouble checkerboard inverted\u201d NoC organization which takes advantage of channel slicing to reduce area while maintaining the performance improvements of the aforementioned techniques. This organization also has a simpler routing mechanism and improves average application throughput per unit area by 24.3%.\n          <\/jats:p>","DOI":"10.1145\/2512429","type":"journal-article","created":{"date-parts":[[2013,9,23]],"date-time":"2013-09-23T13:47:05Z","timestamp":1379944025000},"page":"1-35","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Designing on-chip networks for throughput accelerators"],"prefix":"10.1145","volume":"10","author":[{"given":"Ali","family":"Bakhoda","sequence":"first","affiliation":[{"name":"University of British Columbia, Vancouver, BC, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"John","family":"Kim","sequence":"additional","affiliation":[{"name":"Korea Advanced Institute of Science and Technology, Daejeon, Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tor M.","family":"Aamodt","sequence":"additional","affiliation":[{"name":"University of British Columbia, Vancouver, BC, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2013,9,16]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555810"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the IEEE\/ACM Symposium on Computer Architecture (ISCA'04)","author":"Ahn J. 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