{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:22:45Z","timestamp":1750306965553,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":11,"publisher":"ACM","license":[{"start":{"date-parts":[[2013,9,10]],"date-time":"2013-09-10T00:00:00Z","timestamp":1378771200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2013,9,10]]},"DOI":"10.1145\/2513683.2513686","type":"proceedings-article","created":{"date-parts":[[2013,9,25]],"date-time":"2013-09-25T13:13:17Z","timestamp":1380114797000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA)"],"prefix":"10.1145","author":[{"given":"Vinod","family":"Pangracious","sequence":"first","affiliation":[{"name":"LIP6\/University Pierre and Marie Curie, Paris, VI"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Habib","family":"Mehrez","sequence":"additional","affiliation":[{"name":"LIP6\/University Pierre and Marie Curie, Paris, VI"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Umer","family":"Farooq","sequence":"additional","affiliation":[{"name":"COMSATS IIT Lahore Pakistan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zied","family":"Marrakchi","sequence":"additional","affiliation":[{"name":"FlexRas Technologies, Paris, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,9,10]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.150"},{"key":"e_1_3_2_1_2_1","first-page":"90","article-title":"Through Silicon Via-Based Grid for Thermal Control in 3D Chips","volume":"2","author":"Ayala J. L.","year":"2009","unstructured":"J. L. Ayala , A. Sridhar , V. Pangracious , D. Atienza , and Y. Leblebici . Through Silicon Via-Based Grid for Thermal Control in 3D Chips . Nanonet Switzerland , 2 : 90 -- 98 , June 2009 . J. L. Ayala, A. Sridhar, V. Pangracious, D. Atienza, and Y. Leblebici. Through Silicon Via-Based Grid for Thermal Control in 3D Chips. Nanonet Switzerland, 2:90--98, June 2009.","journal-title":"Nanonet Switzerland"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/1987535.1987565"},{"key":"e_1_3_2_1_4_1","unstructured":"ITRS-2012. International Technology Road Map for Semiconductors-Interconnect TSV Roadmap. http:\/\/public.itrs.net pages 17--21 March 2012.  ITRS-2012. International Technology Road Map for Semiconductors-Interconnect TSV Roadmap. http:\/\/public.itrs.net pages 17--21 March 2012."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1531542.1531603"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117219"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/259837"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-36812-7_19"},{"key":"e_1_3_2_1_9_1","first-page":"123","volume":"97","author":"Pavlidis V.","year":"2009","unstructured":"V. Pavlidis and E. Friedman . Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits. Proceedings of the IEEE , 97 : 123 -- 140 , January 2009 . V. Pavlidis and E. Friedman. Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits. Proceedings of the IEEE, 97:123--140, January 2009.","journal-title":"Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits. Proceedings of the IEEE"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/368640.368739"},{"key":"e_1_3_2_1_11_1","first-page":"132","article-title":"Architecture Level Exploration of Alternative schemes Targeting 3D FPGAs","volume":"25","author":"Siozios K.","year":"2012","unstructured":"K. Siozios , A. Bartzas , and D. Soudris . Architecture Level Exploration of Alternative schemes Targeting 3D FPGAs : A Software Supported Methodology. International Journal of Reconfigurable Computing , 25 : 132 -- 148 , June 2012 . K. Siozios, A. Bartzas, and D. Soudris. Architecture Level Exploration of Alternative schemes Targeting 3D FPGAs: A Software Supported Methodology. International Journal of Reconfigurable Computing, 25:132--148, June 2012.","journal-title":"A Software Supported Methodology. International Journal of Reconfigurable Computing"}],"event":{"name":"FPGAWorld '13: FPGAworld Conference","sponsor":["FPGAworld Academic Conference","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"Stockholm Sweden","acronym":"FPGAWorld '13"},"container-title":["Proceedings of the 10th FPGAworld Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2513683.2513686","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2513683.2513686","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:39:18Z","timestamp":1750235958000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2513683.2513686"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9,10]]},"references-count":11,"alternative-id":["10.1145\/2513683.2513686","10.1145\/2513683"],"URL":"https:\/\/doi.org\/10.1145\/2513683.2513686","relation":{},"subject":[],"published":{"date-parts":[[2013,9,10]]},"assertion":[{"value":"2013-09-10","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}