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Surv."],"published-print":{"date-parts":[[2013,10]]},"abstract":"<jats:p>Networks-on-Chip constitute the interconnection architecture of future, massively parallel multiprocessors that assemble hundreds to thousands of processing cores on a single chip. Their integration is enabled by ongoing miniaturization of chip manufacturing technologies following Moore's Law. It comes with the downside of the circuit elements' increased susceptibility to failure. Research on fault-tolerant Networks-on-Chip tries to mitigate partial failure and its effect on network performance and reliability by exploiting various forms of redundancy at the suitable network layers. The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years. It is structured along three communication layers: the data link, the network, and the transport layers. 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In Proceedings of the 23rd International Fault-Tolerant Computing Digest of Papers Symposium (FTCS'93). 240--249."},{"key":"e_1_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.44"},{"key":"e_1_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2006.46"},{"key":"e_1_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2006.44"},{"key":"e_1_2_1_65_1","volume-title":"IEEE International Electron Devices Meeting Technical Digest (IEDM'03)","author":"Hazucha P.","unstructured":"Hazucha , P. , Karnik , T. , Maiz , J. , Walstra , S. , Bloechel , B. , Tschanz , J. , Dermer , G. , Hareland , S. , Armstrong , P. , and Borkar , S . 2003. Neutron soft error rate measurements in a 90-nm cmos process and scaling trends in sram from 0.25-mu;m to 90-nm generation . In IEEE International Electron Devices Meeting Technical Digest (IEDM'03) . 21.5.1--21.5.4. Hazucha, P., Karnik, T., Maiz, J., Walstra, S., Bloechel, B., Tschanz, J., Dermer, G., Hareland, S., Armstrong, P., and Borkar, S. 2003. Neutron soft error rate measurements in a 90-nm cmos process and scaling trends in sram from 0.25-mu;m to 90-nm generation. In IEEE International Electron Devices Meeting Technical Digest (IEDM'03). 21.5.1--21.5.4."},{"key":"e_1_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.863617"},{"key":"e_1_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2009.5161048"},{"key":"e_1_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.77"},{"key":"e_1_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996638"},{"key":"e_1_2_1_70_1","doi-asserted-by":"crossref","unstructured":"Huffman W. C. and Pless V. 2003. Fundamentals of Error-Correcting Codes. Cambridge University Press. Huffman W. C. and Pless V. 2003. Fundamentals of Error-Correcting Codes. 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International technology roadmap for semiconductors. Tech. rep., ITRS Technology Working Group. http:\/\/www.itrs.net\/Links\/2009ITRS\/2009Chapters_2009Tables\/2009_Interconnect.pdf."},{"key":"e_1_2_1_73_1","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'05)","volume":"2","author":"Jantsch A.","unstructured":"Jantsch , A. , Lauter , R. , and Vitkowski , A . 2005. Power analysis of link level and end-to-end data protection in networks on chip . In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'05) . Vol. 2 . 1770--1773. Jantsch, A., Lauter, R., and Vitkowski, A. 2005. Power analysis of link level and end-to-end data protection in networks on chip. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'05). 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Fault tolerant source routing for network-on-chip . In Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'07) . 12--20. Kim, Y. B. and Kim, Y.-B. 2007. Fault tolerant source routing for network-on-chip. In Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'07). 12--20."},{"key":"e_1_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071441"},{"key":"e_1_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2048399"},{"key":"e_1_2_1_84_1","volume-title":"Proceedings of the 2nd ACM\/IEEE International Symposium on Networks-on-Chip (NoCS'08)","author":"Koibuchi M.","unstructured":"Koibuchi , M. , Matsutani , H. , Amano , H. , and Pinkston , T. M . 2008. A lightweight fault-tolerant mechanism for networkon-chip . In Proceedings of the 2nd ACM\/IEEE International Symposium on Networks-on-Chip (NoCS'08) . 13--22. Koibuchi, M., Matsutani, H., Amano, H., and Pinkston, T. M. 2008. A lightweight fault-tolerant mechanism for networkon-chip. In Proceedings of the 2nd ACM\/IEEE International Symposium on Networks-on-Chip (NoCS'08). 13--22."},{"key":"e_1_2_1_85_1","volume-title":"Proceedings of the World Congress on Engineering and Computer Science.","author":"Koupaei F. K.","unstructured":"Koupaei , F. K. , Khademzadeh , A. , and Janidarmian , M . 2011. Fault-tolerant application-specific network-on-chip . In Proceedings of the World Congress on Engineering and Computer Science. Koupaei, F. K., Khademzadeh, A., and Janidarmian, M. 2011. Fault-tolerant application-specific network-on-chip. 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J."},{"key":"e_1_2_1_87_1","doi-asserted-by":"publisher","DOI":"10.1145\/1255456.1255460"},{"key":"e_1_2_1_88_1","volume-title":"Proceedings of the 2nd International Conference on Nano-Networks (Nano-Net'07)","author":"Lehtonen T.","unstructured":"Lehtonen , T. , Liljeberg , P. , and Plosila , J . 2007a. Analysis of forward error correction methods for nanoscale networks-onchip . In Proceedings of the 2nd International Conference on Nano-Networks (Nano-Net'07) . Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering, 1--5. Lehtonen, T., Liljeberg, P., and Plosila, J. 2007a. Analysis of forward error correction methods for nanoscale networks-onchip. In Proceedings of the 2nd International Conference on Nano-Networks (Nano-Net'07). Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering, 1--5."},{"key":"e_1_2_1_89_1","doi-asserted-by":"publisher","DOI":"10.1155\/2007\/94676"},{"key":"e_1_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2013711"},{"key":"e_1_2_1_91_1","volume-title":"Proceedings of the International Symposium on VLSI Design, Automation and Test (VLSI-DAT'09)","author":"Lin S.-Y.","unstructured":"Lin , S.-Y. , Shen , W.-C. , Hsu , C.-C. , Chao , C.-H. , and Wu , A . -Y. 2009. Fault-tolerant router with built-in self-test\/self-diagnosis and fault-isolation circuits for 2d-mesh based chip multiprocessor systems . In Proceedings of the International Symposium on VLSI Design, Automation and Test (VLSI-DAT'09) . 72--75. Lin, S.-Y., Shen, W.-C., Hsu, C.-C., Chao, C.-H., and Wu, A.-Y. 2009. Fault-tolerant router with built-in self-test\/self-diagnosis and fault-isolation circuits for 2d-mesh based chip multiprocessor systems. In Proceedings of the International Symposium on VLSI Design, Automation and Test (VLSI-DAT'09). 72--75."},{"key":"e_1_2_1_92_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.59"},{"key":"e_1_2_1_93_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.323"},{"key":"e_1_2_1_94_1","unstructured":"Malkin G. and Steenstrup M. 1995. Distance-vector routing. In Routing in Communication Networks M. Steenstrup Ed. Prentice Hall 83--98. Malkin G. and Steenstrup M. 1995. Distance-vector routing. In Routing in Communication Networks M. Steenstrup Ed. Prentice Hall 83--98."},{"key":"e_1_2_1_95_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2010691"},{"key":"e_1_2_1_96_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146959"},{"key":"e_1_2_1_97_1","volume-title":"Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'07)","author":"Mediratta S. D.","unstructured":"Mediratta , S. D. and Draper , J . 2007. Performance evaluation of probe-send fault-tolerant network-on-chip router . In Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'07) . 69--75. Mediratta, S. D. and Draper, J. 2007. Performance evaluation of probe-send fault-tolerant network-on-chip router. In Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'07). 69--75."},{"key":"e_1_2_1_98_1","volume-title":"Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS'06)","author":"Mejia A.","unstructured":"Mejia , A. , Flich , J. , Duato , J. , Reinemo , S.-A. , and Skeie , T . 2006. Segment-based routing: An efficient fault-tolerant routing algorithm for meshes and tori . In Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS'06) . Mejia, A., Flich, J., Duato, J., Reinemo, S.-A., and Skeie, T. 2006. Segment-based routing: An efficient fault-tolerant routing algorithm for meshes and tori. In Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS'06)."},{"key":"e_1_2_1_99_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVSLSI.2008.2012010"},{"key":"e_1_2_1_100_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2100531"},{"key":"e_1_2_1_101_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2003.08.005"},{"key":"e_1_2_1_102_1","volume-title":"Proceedings of the IEEE International Test Conference (ITC'06)","author":"Mitra S.","unstructured":"Mitra , S. , Zhang , M. , Waqas , S. , Seifert , N. , Gill , B. , and Kim , K. S . 2006. Combinational logic soft error correction . In Proceedings of the IEEE International Test Conference (ITC'06) . 1--9. Mitra, S., Zhang, M., Waqas, S., Seifert, N., Gill, B., and Kim, K. S. 2006. Combinational logic soft error correction. In Proceedings of the IEEE International Test Conference (ITC'06). 1--9."},{"key":"e_1_2_1_103_1","volume-title":"Routing in Communication Networks","author":"Moy J.","unstructured":"Moy , J. 1995. Link-state routing . In Routing in Communication Networks , M. Ste, Ed., Prentice Hall , 135--157. Moy, J. 1995. Link-state routing. In Routing in Communication Networks, M. Ste, Ed., Prentice Hall, 135--157."},{"key":"e_1_2_1_104_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147124"},{"key":"e_1_2_1_105_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.104"},{"key":"e_1_2_1_106_1","doi-asserted-by":"publisher","DOI":"10.5555\/832299.836499"},{"key":"e_1_2_1_107_1","doi-asserted-by":"publisher","DOI":"10.1145\/1084834.1084856"},{"key":"e_1_2_1_108_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.91"},{"key":"e_1_2_1_109_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2041851"},{"key":"e_1_2_1_110_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2006.22"},{"key":"e_1_2_1_111_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155668"},{"key":"e_1_2_1_112_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2006.35"},{"key":"e_1_2_1_113_1","volume-title":"Proceedings of the International SoC Design Conference (ISOCC'08)","volume":"1","author":"Patooghy A.","unstructured":"Patooghy , A. and Miremadi , S. G . 2008. Ltr: A low-overhead and reliable routing algorithm for network on chips . In Proceedings of the International SoC Design Conference (ISOCC'08) . Vol. 1 . Patooghy, A. and Miremadi, S. G. 2008. Ltr: A low-overhead and reliable routing algorithm for network on chips. In Proceedings of the International SoC Design Conference (ISOCC'08). Vol. 1."},{"key":"e_1_2_1_114_1","volume-title":"Proceedings of the IEEE International Conference on Computer Design (ICCD'10)","author":"Patooghy A.","unstructured":"Patooghy , A. , Miremadi , S. G. , and Shafaei , M . 2010. Crosstalk modeling to predict channel elay in network-on-chips . In Proceedings of the IEEE International Conference on Computer Design (ICCD'10) . 396--401. Patooghy, A., Miremadi, S. G., and Shafaei, M. 2010. Crosstalk modeling to predict channel elay in network-on-chips. In Proceedings of the IEEE International Conference on Computer Design (ICCD'10). 396--401."},{"key":"e_1_2_1_115_1","volume-title":"Proceedings of the International Symposium on VLSI (ISVLSI'04)","author":"Pirretti M.","unstructured":"Pirretti , M. , Link , G. M. , Brooks , R. R. , Vijaykrishnan , N. , Kandemir , M. T. , and Irwin , M. J . 2004. Fault tolerant algorithms for network-on-chip interconnect . In Proceedings of the International Symposium on VLSI (ISVLSI'04) . IEEE Computer Society, Los Alamitos, CA, 46--51. Pirretti, M., Link, G. M., Brooks, R. R., Vijaykrishnan, N., Kandemir, M. T., and Irwin, M. J. 2004. Fault tolerant algorithms for network-on-chip interconnect. In Proceedings of the International Symposium on VLSI (ISVLSI'04). IEEE Computer Society, Los Alamitos, CA, 46--51."},{"key":"e_1_2_1_116_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.95"},{"key":"e_1_2_1_117_1","doi-asserted-by":"publisher","DOI":"10.1109\/EUC.2011.36"},{"key":"e_1_2_1_118_1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2007.41"},{"key":"e_1_2_1_119_1","volume-title":"Proceedings of the International Symposium on Signals, Circuits and Systems. 1--4.","author":"Rantala V.","unstructured":"Rantala , V. , Lehtonen , T. , Liljeberg , P. , and Plosila , J . 2009. Multi network interface architectures for fault tolerant network-on-chip . In Proceedings of the International Symposium on Signals, Circuits and Systems. 1--4. Rantala, V., Lehtonen, T., Liljeberg, P., and Plosila, J. 2009. Multi network interface architectures for fault tolerant network-on-chip. In Proceedings of the International Symposium on Signals, Circuits and Systems. 1--4."},{"key":"e_1_2_1_120_1","unstructured":"Ravindran D. K. 2009. Structural fault-tolerance on the noc circuit level. Tech. rep. Institut fur Technische Informatik Universitat Stuttgart. June. Ravindran D. K. 2009. Structural fault-tolerance on the noc circuit level. Tech. rep. Institut fur Technische Informatik Universitat Stuttgart. June."},{"key":"e_1_2_1_121_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771805"},{"key":"e_1_2_1_122_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.12"},{"key":"e_1_2_1_123_1","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2007.24"},{"key":"e_1_2_1_124_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.50"},{"key":"e_1_2_1_125_1","unstructured":"Sanyo Semiconductors. 2011. Quality and reliability handbook ver 3. http:\/\/semicon.sanyo.com\/en\/reliability\/. Sanyo Semiconductors. 2011. Quality and reliability handbook ver 3. http:\/\/semicon.sanyo.com\/en\/reliability\/."},{"key":"e_1_2_1_126_1","doi-asserted-by":"publisher","DOI":"10.1109\/49.105178"},{"key":"e_1_2_1_127_1","volume-title":"Proceedings of the International Conference on Computer Aided Design (ICCAD'05)","author":"Schafer M.","unstructured":"Schafer , M. , Hollstein , T. , Zimmer , H. , and Glesner , M . 2005. Deadlock-free routing and component placement for irregular mesh-based networks-on-chip . In Proceedings of the International Conference on Computer Aided Design (ICCAD'05) . 238--245. Schafer, M., Hollstein, T., Zimmer, H., and Glesner, M. 2005. Deadlock-free routing and component placement for irregular mesh-based networks-on-chip. In Proceedings of the International Conference on Computer Aided Design (ICCAD'05). 238--245."},{"key":"e_1_2_1_128_1","doi-asserted-by":"publisher","DOI":"10.5555\/1302494.1302854"},{"key":"e_1_2_1_129_1","volume-title":"Proceedings of the International Test Conference.","author":"Shamshiri S.","unstructured":"Shamshiri , S. , Ghofrani , A. , and Cheng , K . -T. 2011. End-to-end error correction and online diagnosis for on-chip networks . In Proceedings of the International Test Conference. Shamshiri, S., Ghofrani, A., and Cheng, K.-T. 2011. End-to-end error correction and online diagnosis for on-chip networks. In Proceedings of the International Test Conference."},{"key":"e_1_2_1_130_1","volume-title":"Proceedings of the International Conference on Dependable Systems and Networks.","author":"Shivakumar P.","unstructured":"Shivakumar , P. , Kistler , M. , Keckler , S. W. , Burger , D. , and Alvisi , L . 2002. Modeling the effect of technology trends on the soft error rate of combinational logic . In Proceedings of the International Conference on Dependable Systems and Networks. Shivakumar, P., Kistler, M., Keckler, S. W., Burger, D., and Alvisi, L. 2002. Modeling the effect of technology trends on the soft error rate of combinational logic. In Proceedings of the International Conference on Dependable Systems and Networks."},{"key":"e_1_2_1_131_1","volume-title":"Reliability of Computer Systems and Networks: Fault Tolerance, Analysis, and Design","author":"Shooman M. L.","unstructured":"Shooman , M. L. 2002. Reliability of Computer Systems and Networks: Fault Tolerance, Analysis, and Design . John Wiley & Sons . Shooman, M. L. 2002. Reliability of Computer Systems and Networks: Fault Tolerance, Analysis, and Design. John Wiley & Sons."},{"key":"e_1_2_1_132_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071442"},{"key":"e_1_2_1_133_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.848816"},{"key":"e_1_2_1_134_1","volume-title":"Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modelling and Simulation.","author":"Strano A.","unstructured":"Strano , A. , Bertozzi , D. , Trivino , F. , Sanchez , J. L. , Alfaro , F. J. , and Flich , J . 2012. Osr-lite: Fast and deadlock-free noc reconfiguration framework . In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modelling and Simulation. Strano, A., Bertozzi, D., Trivino, F., Sanchez, J. L., Alfaro, F. J., and Flich, J. 2012. Osr-lite: Fast and deadlock-free noc reconfiguration framework. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modelling and Simulation."},{"key":"e_1_2_1_135_1","unstructured":"Takeda E. and Yang C. 1995. Hot-Carrier Effects in MOS Devices. Academic Press. Takeda E. and Yang C. 1995. Hot-Carrier Effects in MOS Devices. Academic Press."},{"key":"e_1_2_1_136_1","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1121009"},{"key":"e_1_2_1_137_1","volume-title":"Digest of Technical Papers of the IEEE International Solid-State Circuits Conference (ISSCC'07)","author":"Vangal S.","unstructured":"Vangal , S. , Howard , J. , Ruhl , G. , Dighe , S. , Wilson , H. , Tschanz , J. , Finan , D. , Iyer , P. , Singh , A. , Jacob , T. , Jain , S. , Venkataraman , S. , Hoskote , Y. , and Borkar , N . 2007. An 80-tile 1.28tflops network-on-chip in 65nm cmos . In Digest of Technical Papers of the IEEE International Solid-State Circuits Conference (ISSCC'07) . 98--589. Vangal, S., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Iyer, P., Singh, A., Jacob, T., Jain, S., Venkataraman, S., Hoskote, Y., and Borkar, N. 2007. An 80-tile 1.28tflops network-on-chip in 65nm cmos. In Digest of Technical Papers of the IEEE International Solid-State Circuits Conference (ISSCC'07). 98--589."},{"key":"e_1_2_1_138_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1971.1090700"},{"key":"e_1_2_1_139_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt:20050060"},{"key":"e_1_2_1_140_1","volume-title":"Proceedings of the IEEE International Computer Design Conference (ICCD'10)","author":"Vitkovskiy A.","unstructured":"Vitkovskiy , A. , Soteriou , V. , and Nicopoulos , C . 2010. A fine-grained link-level fault-tolerant mechanism for networks-onchip . In Proceedings of the IEEE International Computer Design Conference (ICCD'10) . 447--454. Vitkovskiy, A., Soteriou, V., and Nicopoulos, C. 2010. A fine-grained link-level fault-tolerant mechanism for networks-onchip. In Proceedings of the IEEE International Computer Design Conference (ICCD'10). 447--454."},{"key":"e_1_2_1_141_1","doi-asserted-by":"publisher","DOI":"10.1109\/6.825662"},{"key":"e_1_2_1_142_1","volume-title":"Proceedings of the Nanotechnology Conference.","author":"Wittmann R.","unstructured":"Wittmann , R. , Puchner , H. , Hinh , L. , Ceric , H. , Gehring , A. , and Selberherr , S . 2005. Simulation of dynamic nbti degradation for a 90nm cmos technology . In Proceedings of the Nanotechnology Conference. Wittmann, R., Puchner, H., Hinh, L., Ceric, H., Gehring, A., and Selberherr, S. 2005. Simulation of dynamic nbti degradation for a 90nm cmos technology. In Proceedings of the Nanotechnology Conference."},{"key":"e_1_2_1_143_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9317(01)00629-3"},{"key":"e_1_2_1_144_1","volume-title":"Proceedings of the International Conference on Parallel Processing. 247--254","author":"Wu J.","unstructured":"Wu , J. and Wang , D . 2002. Fault-tolerant and deadlock-free routing in 2-d meshes using rectilinear-monotone polygonal fault blocks . In Proceedings of the International Conference on Parallel Processing. 247--254 . Wu, J. and Wang, D. 2002. Fault-tolerant and deadlock-free routing in 2-d meshes using rectilinear-monotone polygonal fault blocks. In Proceedings of the International Conference on Parallel Processing. 247--254."},{"key":"e_1_2_1_145_1","volume-title":"Proceedings of the 2nd International Computer Engineering and Technology Conference (ICCET'10)","author":"Xinming D.","unstructured":"Xinming , D. and Xuemei , S . 2010. Fault-tolerant routing in a prdt(2,1)-based noc . In Proceedings of the 2nd International Computer Engineering and Technology Conference (ICCET'10) . Xinming, D. and Xuemei, S. 2010. Fault-tolerant routing in a prdt(2,1)-based noc. In Proceedings of the 2nd International Computer Engineering and Technology Conference (ICCET'10)."},{"key":"e_1_2_1_146_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2010.10.003"},{"key":"e_1_2_1_148_1","volume-title":"Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT'05)","author":"Yu A. J.","unstructured":"Yu , A. J. and Lemieux , G. G . 2005. Fpga defect tolerance: Impact of granularity . In Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT'05) . 189--196. Yu, A. J. and Lemieux, G. G. 2005. Fpga defect tolerance: Impact of granularity. In Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT'05). 189--196."},{"key":"e_1_2_1_149_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2008.40"},{"key":"e_1_2_1_150_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.24"},{"key":"e_1_2_1_151_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2092817"},{"key":"e_1_2_1_152_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2156436"},{"key":"e_1_2_1_153_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.27"},{"key":"e_1_2_1_154_1","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'10)","author":"Yu Q.","unstructured":"Yu , Q. , Zhang , B. , Li , Y. , and Ampadu , P . 2010. Error control integration scheme for reliable noc . In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'10) . 3893--3896. Yu, Q., Zhang, B., Li, Y., and Ampadu, P. 2010. Error control integration scheme for reliable noc. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'10). 3893--3896."},{"key":"e_1_2_1_155_1","doi-asserted-by":"publisher","DOI":"10.1145\/1999946.1999964"},{"key":"e_1_2_1_156_1","volume-title":"Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED'08)","author":"Zhang B.","unstructured":"Zhang , B. and Orshansky , M . 2008. Modeling of nbti-induced pmos degradation under arbitrary dynamic temperature variation . In Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED'08) . 774--779. Zhang, B. and Orshansky, M. 2008. Modeling of nbti-induced pmos degradation under arbitrary dynamic temperature variation. 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