{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:20:41Z","timestamp":1750306841523,"version":"3.41.0"},"reference-count":11,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2013,12,1]],"date-time":"2013-12-01T00:00:00Z","timestamp":1385856000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001738","name":"Israel Ministry of Science, Technology and Space","doi-asserted-by":"crossref","award":["Mar-96"],"award-info":[{"award-number":["Mar-96"]}],"id":[{"id":"10.13039\/501100001738","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2013,12]]},"abstract":"<jats:p>\n            We consider the problem of synthesizing circuits (from C to Verilog) that are optimized to handle unpredictable latencies of memory operations. Unpredictable memory latencies can occur due to the use of on chip caches, DRAM memory modules, buffers\/queues, or multiport memories. Typically, high-level synthesis compilers assume fixed and known memory latencies, and thus are able to schedule the code\u2019s operations efficiently. The operations in the source code are scheduled into states of a state machine whose states will be synthesized to Verilog. The goal is to minimize scheduling length by maximizing the number of operations (and in particular memory operations) that are executed in parallel at the same state. However, with unpredictable latencies, there can be an exponential number of possible orders in which these parallel memory operations can terminate. Thus, in order to minimize the scheduling, we need a different schedule for any such order. This is not practical, and we show a technique of synthesizing a\n            <jats:italic>compact<\/jats:italic>\n            state machine that schedules only a small subset of these possible termination orders. Our results show that this compact state machine can improve the execution time compared to a regular scheduling that waits for the termination of all the active memory references in every state.\n          <\/jats:p>","DOI":"10.1145\/2535936","type":"journal-article","created":{"date-parts":[[2013,12,20]],"date-time":"2013-12-20T19:50:46Z","timestamp":1387569046000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Optimizing Wait States in the Synthesis of Memory References with Unpredictable Latencies"],"prefix":"10.1145","volume":"6","author":[{"given":"Yosi","family":"Ben-Asher","sequence":"first","affiliation":[{"name":"University of Haifa"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ron","family":"Meldiner","sequence":"additional","affiliation":[{"name":"University of Haifa"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nadav","family":"Rotem","sequence":"additional","affiliation":[{"name":"University of Haifa"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,12]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Brock B. and Exerman M. 2006. Cache latencies of the powerpc mpc7451. Freescale Semiconductor Application Note AN2180.  Brock B. and Exerman M. 2006. Cache latencies of the powerpc mpc7451. Freescale Semiconductor Application Note AN2180."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147077"},{"volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, 1779--1784","author":"Del Barrio A.","key":"e_1_2_1_3_1"},{"key":"e_1_2_1_4_1","unstructured":"Devadas S. Ghosh A. and Keutzer K. 1994. Logic Synthesis. McGraw-Hill.   Devadas S. Ghosh A. and Keutzer K. 1994. Logic Synthesis . McGraw-Hill."},{"key":"e_1_2_1_5_1","unstructured":"Gajski D. 1996. Principles of Digital Design. Prentice-Hall Inc.   Gajski D. 1996. Principles of Digital Design . Prentice-Hall Inc."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.137516"},{"key":"e_1_2_1_7_1","unstructured":"Lattner C. and Adve V. 2002. The LLVM instruction set and compilation strategy. Tech. rep. UIUCDCS-R-2002-2292 University of Illinois at Urbana-Champaign.  Lattner C. and Adve V. 2002. The LLVM instruction set and compilation strategy. Tech. rep. UIUCDCS-R-2002-2292 University of Illinois at Urbana-Champaign."},{"key":"e_1_2_1_8_1","unstructured":"McMahon F. 1986. The Livermore Fortran kernels: A computer test of the numerical performance range. Tech. rep. UCRL-53746 Lawrence Livermore National Laboratory Livermore CA.  McMahon F. 1986. The Livermore Fortran kernels: A computer test of the numerical performance range. Tech. rep. UCRL-53746 Lawrence Livermore National Laboratory Livermore CA."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.681260"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.875270"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.386007"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2535936","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2535936","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:10:06Z","timestamp":1750234206000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2535936"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12]]},"references-count":11,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2013,12]]}},"alternative-id":["10.1145\/2535936"],"URL":"https:\/\/doi.org\/10.1145\/2535936","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2013,12]]},"assertion":[{"value":"2012-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-12-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}