{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:50:22Z","timestamp":1750308622066,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":16,"publisher":"ACM","license":[{"start":{"date-parts":[[2013,12,8]],"date-time":"2013-12-08T00:00:00Z","timestamp":1386460800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2013,12,8]]},"DOI":"10.1145\/2536522.2536526","type":"proceedings-article","created":{"date-parts":[[2013,12,17]],"date-time":"2013-12-17T13:36:21Z","timestamp":1387287381000},"page":"41-46","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Costs and benefits of flexibility in spatial division circuit switched networks-on-chip"],"prefix":"10.1145","author":[{"given":"Ahsen","family":"Ejaz","sequence":"first","affiliation":[{"name":"Royal Institute of Technology, Sweden"}]},{"given":"Axel","family":"Jantsch","sequence":"additional","affiliation":[{"name":"Royal Institute of Technology, Sweden"}]}],"member":"320","published-online":{"date-parts":[[2013,12,8]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"KTH","author":"Vali A.","year":"2011","unstructured":"A. Vali , \"Design and Implementation of a Multi Channel Circuit-Switched Network-on-Chip,\" Master's Thesis at ICT , KTH , Stockholm , 2011 . A. Vali, \"Design and Implementation of a Multi Channel Circuit-Switched Network-on-Chip,\" Master's Thesis at ICT, KTH, Stockholm, 2011."},{"key":"e_1_3_2_1_2_1","volume-title":"Guaranteed service virtual channel allocation in NoCs for run-time task scheduling,\" in DATE Conference","author":"Winter M.","year":"2011","unstructured":"M. Winter and G. Fettweis , \" Guaranteed service virtual channel allocation in NoCs for run-time task scheduling,\" in DATE Conference , 2011 . M. Winter and G. Fettweis, \"Guaranteed service virtual channel allocation in NoCs for run-time task scheduling,\" in DATE Conference, 2011."},{"key":"e_1_3_2_1_3_1","volume-title":"Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC,\" in DATE Conference","author":"Liu S.","year":"2012","unstructured":"S. Liu , A. Jantsch and Z. Lu , \" Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC,\" in DATE Conference , 2012 . S. Liu, A. Jantsch and Z. Lu, \"Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC,\" in DATE Conference, 2012."},{"key":"e_1_3_2_1_4_1","volume-title":"A hybrid NoC combining SDM-TDM based circuit-switching with packet-switching for real-time applications,\" in IEEE 10th International New Circuits and Systems Conference (NEWCAS)","author":"Lusala A. K.","year":"2012","unstructured":"A. K. Lusala and J. Legat , \" A hybrid NoC combining SDM-TDM based circuit-switching with packet-switching for real-time applications,\" in IEEE 10th International New Circuits and Systems Conference (NEWCAS) , 2012 . A. K. Lusala and J. Legat, \"A hybrid NoC combining SDM-TDM based circuit-switching with packet-switching for real-time applications,\" in IEEE 10th International New Circuits and Systems Conference (NEWCAS), 2012."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1084834.1084858"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2013.13"},{"key":"e_1_3_2_1_7_1","volume-title":"The Nostrum backbone-a communication protocol stack for Networks on Chip,\" in 17th International Conference on VLSI Design","author":"Millberg M.","year":"2004","unstructured":"M. Millberg , E. Nilsson , R. Thid , S. Kumar and A. Jantsch , \" The Nostrum backbone-a communication protocol stack for Networks on Chip,\" in 17th International Conference on VLSI Design , 2004 . M. Millberg, E. Nilsson, R. Thid, S. Kumar and A. Jantsch, \"The Nostrum backbone-a communication protocol stack for Networks on Chip,\" in 17th International Conference on VLSI Design, 2004."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278510"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.99"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146950"},{"key":"e_1_3_2_1_11_1","volume-title":"IEEE International","author":"Deivasigamani M.","year":"2011","unstructured":"M. Deivasigamani , S. Tabatabaei , N. Mustafa , H. Ijaz , H. Aslam , S. Liu and A. Jantsch , \" Concept and design of exhaustive-parallel search algorithm for Network-on-Chip,\" in SOC Conference (SOCC) , IEEE International , 2011 . M. Deivasigamani, S. Tabatabaei, N. Mustafa, H. Ijaz, H. Aslam, S. Liu and A. Jantsch, \"Concept and design of exhaustive-parallel search algorithm for Network-on-Chip,\" in SOC Conference (SOCC), IEEE International, 2011."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.82"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.95"},{"key":"e_1_3_2_1_14_1","volume-title":"A hybrid NoC combining SDM-based circuit switching with packet switching for real-time applications,\" in NORCHIP","author":"Lusala A.","year":"2010","unstructured":"A. Lusala and J. Legat , \" A hybrid NoC combining SDM-based circuit switching with packet switching for real-time applications,\" in NORCHIP , 2010 . A. Lusala and J. Legat, \"A hybrid NoC combining SDM-based circuit switching with packet switching for real-time applications,\" in NORCHIP, 2010."},{"key":"e_1_3_2_1_15_1","unstructured":"A. Ejaz \"Enhancement and Evaluation of Multi-Channel Circuit Switched Network on Chip \" Masters Thesis at ICT KTH Stockholm 2013.  A. Ejaz \"Enhancement and Evaluation of Multi-Channel Circuit Switched Network on Chip \" Masters Thesis at ICT KTH Stockholm 2013."},{"key":"e_1_3_2_1_16_1","volume-title":"Digital integrated circuits - A design perspective","author":"Rabaey J. M.","year":"2002","unstructured":"J. M. Rabaey , A. Chandrakasan and B. Nikolic , Digital integrated circuits - A design perspective , 2 nd ed., 2002 . J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital integrated circuits - A design perspective, 2nd ed., 2002.","edition":"2"}],"event":{"name":"NoCArc '13: Network on Chip Architectures","acronym":"NoCArc '13","location":"Davis California USA"},"container-title":["Proceedings of the Sixth International Workshop on Network on Chip Architectures"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2536522.2536526","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2536522.2536526","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T19:07:41Z","timestamp":1750273661000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2536522.2536526"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12,8]]},"references-count":16,"alternative-id":["10.1145\/2536522.2536526","10.1145\/2536522"],"URL":"https:\/\/doi.org\/10.1145\/2536522.2536526","relation":{},"subject":[],"published":{"date-parts":[[2013,12,8]]},"assertion":[{"value":"2013-12-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}