{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,2]],"date-time":"2026-01-02T07:46:34Z","timestamp":1767339994558,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":47,"publisher":"ACM","license":[{"start":{"date-parts":[[2013,12,7]],"date-time":"2013-12-07T00:00:00Z","timestamp":1386374400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1216611"],"award-info":[{"award-number":["1216611"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100006112","name":"Microsoft Research","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006112","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100005801","name":"Facebook","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100005801","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2013,12,7]]},"DOI":"10.1145\/2540708.2540712","type":"proceedings-article","created":{"date-parts":[[2013,12,17]],"date-time":"2013-12-17T13:36:21Z","timestamp":1387287381000},"page":"25-36","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":166,"title":["Approximate storage in solid-state memories"],"prefix":"10.1145","author":[{"given":"Adrian","family":"Sampson","sequence":"first","affiliation":[{"name":"University of Washington"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jacob","family":"Nelson","sequence":"additional","affiliation":[{"name":"University of Washington"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Karin","family":"Strauss","sequence":"additional","affiliation":[{"name":"Microsoft Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luis","family":"Ceze","sequence":"additional","affiliation":[{"name":"University of Washington"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,12,7]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"UCI machine learning repository","author":"Bache K.","year":"2013","unstructured":"K. Bache and M. Lichman , \" UCI machine learning repository ,\" 2013 . {Online}. Available: http:\/\/archive.ics.uci.edu\/ml K. Bache and M. Lichman, \"UCI machine learning repository,\" 2013. {Online}. Available: http:\/\/archive.ics.uci.edu\/ml"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1806596.1806620"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2062185"},{"key":"e_1_3_2_1_4_1","volume-title":"Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis,\" in DATE","author":"Cai Y.","year":"2012","unstructured":"Y. Cai , E. Haratsch , O. Mutlu , and K. Mai , \" Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis,\" in DATE , 2012 . Y. Cai, E. Haratsch, O. Mutlu, and K. Mai, \"Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis,\" in DATE, 2012."},{"key":"e_1_3_2_1_5_1","volume-title":"Reasoning about relaxed programs,\" in PLDI","author":"Carbin M.","year":"2012","unstructured":"M. Carbin , D. Kim , S. Misailovic , and M. C. Rinard , \" Reasoning about relaxed programs,\" in PLDI , 2012 . M. Carbin, D. Kim, S. Misailovic, and M. C. Rinard, \"Reasoning about relaxed programs,\" in PLDI, 2012."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2509136.2509546"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.33"},{"key":"e_1_3_2_1_8_1","volume-title":"Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology,\" in DATE","author":"Chakrapani L. N.","year":"2006","unstructured":"L. N. Chakrapani , B. E. S. Akgul , S. Cheemalavagu , P. Korkmaz , K. V. Palem , and B. Seshasayee , \" Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology,\" in DATE , 2006 . L. N. Chakrapani, B. E. S. Akgul, S. Cheemalavagu, P. Korkmaz, K. V. Palem, and B. Seshasayee, \"Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology,\" in DATE, 2006."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2011.2105550"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950380"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485961"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816026"},{"key":"e_1_3_2_1_13_1","volume-title":"AdaMS: Adaptive MLC\/SLC phase-change memory design for file storage,\" in Asia and South Pacific Design Automation Conference","author":"Dong X.","year":"2011","unstructured":"X. Dong and Y. Xie , \" AdaMS: Adaptive MLC\/SLC phase-change memory design for file storage,\" in Asia and South Pacific Design Automation Conference , 2011 . X. Dong and Y. Xie, \"AdaMS: Adaptive MLC\/SLC phase-change memory design for file storage,\" in Asia and South Pacific Design Automation Conference, 2011."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151008"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.48"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155642"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950390"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736023"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169027"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810392"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555758"},{"key":"e_1_3_2_1_22_1","volume-title":"ERSA: Error resilient system architecture for probabilistic applications,\" in DATE","author":"Leem L.","year":"2010","unstructured":"L. Leem , H. Cho , J. Bau , Q. A. Jacobson , and S. Mitra , \" ERSA: Error resilient system architecture for probabilistic applications,\" in DATE , 2010 . L. Leem, H. Cho, J. Bau, Q. A. Jacobson, and S. Mitra, \"ERSA: Error resilient system architecture for probabilistic applications,\" in DATE, 2010."},{"key":"e_1_3_2_1_23_1","volume-title":"Optimizing NAND flash-based SSDs via retention relaxation,\" in FAST","author":"Liu R.-S.","year":"2012","unstructured":"R.-S. Liu , C.-L. Yang , and W. Wu , \" Optimizing NAND flash-based SSDs via retention relaxation,\" in FAST , 2012 . R.-S. Liu, C.-L. Yang, and W. Wu, \"Optimizing NAND flash-based SSDs via retention relaxation,\" in FAST, 2012."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950391"},{"key":"e_1_3_2_1_25_1","volume-title":"Bit error rate in NAND flash memories,\" in International Reliability Physics Symposium","author":"Mielke N.","year":"2008","unstructured":"N. Mielke , T. Marquart , N. Wu , J. Kessenich , H. Belgal , E. Schares , F. Trivedi , E. Goodness , and L. Nevill , \" Bit error rate in NAND flash memories,\" in International Reliability Physics Symposium , 2008 . N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, E. Schares, F. Trivedi, E. Goodness, and L. Nevill, \"Bit error rate in NAND flash memories,\" in International Reliability Physics Symposium, 2008."},{"key":"e_1_3_2_1_26_1","volume-title":"Scalable stochastic processors,\" in DATE","author":"Narayanan S.","year":"2010","unstructured":"S. Narayanan , J. Sartori , R. Kumar , and D. L. Jones , \" Scalable stochastic processors,\" in DATE , 2010 . S. Narayanan, J. Sartori, R. Kumar, and D. L. Jones, \"Scalable stochastic processors,\" in DATE, 2010."},{"key":"e_1_3_2_1_27_1","volume-title":"Write strategies for 2 and 4-bit multi-level phase-change memory,\" in IEDM","author":"Nirschl T.","year":"2007","unstructured":"T. Nirschl , J. Phipp , T. Happ , G. Burr , B. Rajendran , M.-H. Lee , A. Schrott , M. Yang , M. Breitwisch , C.-F. Chen , E. Joseph , M. Lamorey , R. Cheek , S.-H. Chen , S. Zaidi , S. Raoux , Y. Chen , Y. Zhu , R. Bergmann , H.-L. Lung , and C. Lam , \" Write strategies for 2 and 4-bit multi-level phase-change memory,\" in IEDM , 2007 . T. Nirschl, J. Phipp, T. Happ, G. Burr, B. Rajendran, M.-H. Lee, A. Schrott, M. Yang, M. Breitwisch, C.-F. Chen, E. Joseph, M. Lamorey, R. Cheek, S.-H. Chen, S. Zaidi, S. Raoux, Y. Chen, Y. Zhu, R. Bergmann, H.-L. Lung, and C. Lam, \"Write strategies for 2 and 4-bit multi-level phase-change memory,\" in IEDM, 2007."},{"key":"e_1_3_2_1_28_1","volume-title":"Multilevel phase change memory modeling and experimental characterization,\" EPCOS","author":"Pantazi A.","year":"2009","unstructured":"A. Pantazi , A. Sebastian , N. Papandreou , M. Breitwisch , C. Lam , H. Pozidis , and E. Eleftheriou , \" Multilevel phase change memory modeling and experimental characterization,\" EPCOS , 2009 . A. Pantazi, A. Sebastian, N. Papandreou, M. Breitwisch, C. Lam, H. Pozidis, and E. Eleftheriou, \"Multilevel phase change memory modeling and experimental characterization,\" EPCOS, 2009."},{"key":"e_1_3_2_1_29_1","volume-title":"Multilevel phase-change memory,\" in IEEE International Conference on Electronics, Circuits, and Systems","author":"Papandreou N.","year":"2010","unstructured":"N. Papandreou , A. Pantazi , A. Sebastian , M. Breitwisch , C. Lam , H. Pozidis , and E. Eleftheriou , \" Multilevel phase-change memory,\" in IEEE International Conference on Electronics, Circuits, and Systems , 2010 . N. Papandreou, A. Pantazi, A. Sebastian, M. Breitwisch, C. Lam, H. Pozidis, and E. Eleftheriou, \"Multilevel phase-change memory,\" in IEEE International Conference on Electronics, Circuits, and Systems, 2010."},{"key":"e_1_3_2_1_30_1","volume-title":"Drift-tolerant multilevel phase-change memory,\" in IEEE International Memory Workshop","author":"Papandreou N.","year":"2011","unstructured":"N. Papandreou , H. Pozidis , T. Mittelholzer , G. Close , M. Breitwisch , C. Lam , and E. Eleftheriou , \" Drift-tolerant multilevel phase-change memory,\" in IEEE International Memory Workshop , 2011 . N. Papandreou, H. Pozidis, T. Mittelholzer, G. Close, M. Breitwisch, C. Lam, and E. Eleftheriou, \"Drift-tolerant multilevel phase-change memory,\" in IEEE International Memory Workshop, 2011."},{"key":"e_1_3_2_1_31_1","first-page":"329","article-title":"Programming algorithms for multilevel phase-change memory","author":"Papandreou N.","year":"2011","unstructured":"N. Papandreou , H. Pozidis , A. Pantazi , A. Sebastian , M. Breitwisch , C. Lam , and E. Eleftheriou , \" Programming algorithms for multilevel phase-change memory ,\" in ISCAS , 2011 , pp. 329 -- 332 . N. Papandreou, H. Pozidis, A. Pantazi, A. Sebastian, M. Breitwisch, C. Lam, and E. Eleftheriou, \"Programming algorithms for multilevel phase-change memory,\" in ISCAS, 2011, pp. 329--332.","journal-title":"ISCAS"},{"key":"e_1_3_2_1_32_1","volume-title":"A framework for reliability assessment in multilevel phase-change memory,\" in IEEE International Memory Workshop","author":"Pozidis H.","year":"2012","unstructured":"H. Pozidis , N. Papandreou , A. Sebastian , T. Mittelholzer , M. BrightSky , C. Lam , and E. Eleftheriou , \" A framework for reliability assessment in multilevel phase-change memory,\" in IEEE International Memory Workshop , 2012 . H. Pozidis, N. Papandreou, A. Sebastian, T. Mittelholzer, M. BrightSky, C. Lam, and E. Eleftheriou, \"A framework for reliability assessment in multilevel phase-change memory,\" in IEEE International Memory Workshop, 2012."},{"key":"e_1_3_2_1_33_1","volume-title":"Improving read performance of phase change memories via write cancellation and write pausing,\" in HPCA","author":"Qureshi M. K.","year":"2010","unstructured":"M. K. Qureshi , M. M. Franceschini , and L. A. Lastras-Montano , \" Improving read performance of phase change memories via write cancellation and write pausing,\" in HPCA , 2010 . M. K. Qureshi, M. M. Franceschini, and L. A. Lastras-Montano, \"Improving read performance of phase change memories via write cancellation and write pausing,\" in HPCA, 2010."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155658"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815981"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555760"},{"key":"e_1_3_2_1_37_1","volume-title":"Exploiting half-wits: Smarter storage for low-power devices,\" in FAST","author":"Salajegheh M.","year":"2011","unstructured":"M. Salajegheh , Y. Wang , K. Fu , A. Jiang , and E. Learned-Miller , \" Exploiting half-wits: Smarter storage for low-power devices,\" in FAST , 2011 . M. Salajegheh, Y. Wang, K. Fu, A. Jiang, and E. Learned-Miller, \"Exploiting half-wits: Smarter storage for low-power devices,\" in FAST, 2011."},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993518"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815980"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.46"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/2025113.2025133"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.475701"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.705361"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488935"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/1961295.1950379"},{"key":"e_1_3_2_1_46_1","volume-title":"Deconstructing and Debunking","author":"Yeo S.","year":"2012","unstructured":"S. Yeo , N. H. Seong , and H.-H. S. Lee , \"Can multi-level cell PCM be reliable and usable? Analyzing the impact of resistance drift,\" in Workshop on Duplicating , Deconstructing and Debunking , 2012 . S. Yeo, N. H. Seong, and H.-H. S. Lee, \"Can multi-level cell PCM be reliable and usable? Analyzing the impact of resistance drift,\" in Workshop on Duplicating, Deconstructing and Debunking, 2012."},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555759"}],"event":{"name":"MICRO-46: The 46th Annual IEEE\/ACM International Symposium on Microarchitecture","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE CS"],"location":"Davis California","acronym":"MICRO-46"},"container-title":["Proceedings of the 46th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2540708.2540712","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2540708.2540712","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:10:33Z","timestamp":1750234233000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2540708.2540712"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12,7]]},"references-count":47,"alternative-id":["10.1145\/2540708.2540712","10.1145\/2540708"],"URL":"https:\/\/doi.org\/10.1145\/2540708.2540712","relation":{},"subject":[],"published":{"date-parts":[[2013,12,7]]},"assertion":[{"value":"2013-12-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}