{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,27]],"date-time":"2026-01-27T12:34:20Z","timestamp":1769517260004,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":38,"publisher":"ACM","license":[{"start":{"date-parts":[[2013,12,7]],"date-time":"2013-12-07T00:00:00Z","timestamp":1386374400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000144","name":"Division of Computer and Network Systems","doi-asserted-by":"publisher","award":["CNS-0916725, CCF-1017650, CNS-1117280, CCF-1218323"],"award-info":[{"award-number":["CNS-0916725, CCF-1017650, CNS-1117280, CCF-1218323"]}],"id":[{"id":"10.13039\/100000144","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CNS-0916725, CCF-1017650, CNS-1117280, CCF-1218323"],"award-info":[{"award-number":["CNS-0916725, CCF-1017650, CNS-1117280, CCF-1218323"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100007015","name":"University of Wisconsin-Madison","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100007015","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2013,12,7]]},"DOI":"10.1145\/2540708.2540715","type":"proceedings-article","created":{"date-parts":[[2013,12,17]],"date-time":"2013-12-17T13:36:21Z","timestamp":1387287381000},"page":"62-73","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":67,"title":["Decoupled compressed cache"],"prefix":"10.1145","author":[{"given":"Somayeh","family":"Sardashti","sequence":"first","affiliation":[{"name":"University of Wisconsin-Madison"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David A.","family":"Wood","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,12,7]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Proceedings of the 7th IEEE Symposium on High-Performance Computer Architecture.","author":"Abali B.","unstructured":"Abali , B. et al. 2001. Performance of Hardware Compressed Main Memory . In Proceedings of the 7th IEEE Symposium on High-Performance Computer Architecture. Abali, B. et al. 2001. Performance of Hardware Compressed Main Memory. In Proceedings of the 7th IEEE Symposium on High-Performance Computer Architecture."},{"key":"e_1_3_2_1_2_1","volume-title":"Proceedings of the 31st Annual International Symposium on Computer Architecture.","author":"Alameldeen A.","unstructured":"Alameldeen , A. and Wood , D . 2004. Adaptive Cache Compression for High-Performance Processors . In Proceedings of the 31st Annual International Symposium on Computer Architecture. Alameldeen, A. and Wood, D. 2004. Adaptive Cache Compression for High-Performance Processors. In Proceedings of the 31st Annual International Symposium on Computer Architecture."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1178046"},{"key":"e_1_3_2_1_4_1","volume-title":"Proceedings of the Ninth IEEE Symposium on High-Performance Computer Architecture.","author":"Alameldeen A.","unstructured":"Alameldeen , A. and Wood , D . 2003. Variability in Architectural Simulations of Multi-threaded Workloads . In Proceedings of the Ninth IEEE Symposium on High-Performance Computer Architecture. Alameldeen, A. and Wood, D. 2003. Variability in Architectural Simulations of Multi-threaded Workloads. In Proceedings of the Ninth IEEE Symposium on High-Performance Computer Architecture."},{"key":"e_1_3_2_1_5_1","volume-title":"A Case for a Value-Aware Cache","author":"Arelakis A.","unstructured":"Arelakis , A. , Stenstr\u00f6m , P. 2012. A Case for a Value-Aware Cache . IEEE Computer Architecture Letters . Arelakis, A., Stenstr\u00f6m, P. 2012. A Case for a Value-Aware Cache. IEEE Computer Architecture Letters."},{"key":"e_1_3_2_1_6_1","volume-title":"SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance. In Workshop on OpenMP Applications and Tools.","author":"Aslot V.","unstructured":"Aslot , V. et al. 2001 . SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance. In Workshop on OpenMP Applications and Tools. Aslot, V. et al. 2001. SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance. In Workshop on OpenMP Applications and Tools."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522313"},{"key":"e_1_3_2_1_8_1","volume-title":"Workshop on Modeling, Benchmarking and Simulation.","author":"Bienia C.","unstructured":"Bienia , C. et al. 2009. PARSEC 2.0: A New Benchmark Suite for Chip-Multiprocessors . In Workshop on Modeling, Benchmarking and Simulation. Bienia, C. et al. 2009. PARSEC 2.0: A New Benchmark Suite for Chip-Multiprocessors. In Workshop on Modeling, Benchmarking and Simulation."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2020989"},{"key":"e_1_3_2_1_10_1","unstructured":"Intel Core i7 Processors http:\/\/www.intel.com\/products\/processor\/corei7\/  Intel Core i7 Processors http:\/\/www.intel.com\/products\/processor\/corei7\/"},{"key":"e_1_3_2_1_11_1","volume-title":"International Symposium on High Performance Computer Architecture.","author":"Das R.","unstructured":"Das , R. et al. 2008. Performance and Power Optimization through Data Compression in Network-on-Chip Architectures , International Symposium on High Performance Computer Architecture. Das, R. et al. 2008. Performance and Power Optimization through Data Compression in Network-on-Chip Architectures, International Symposium on High Performance Computer Architecture."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1944862.1944876"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542288"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1080695.1069978"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.4"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339660"},{"key":"e_1_3_2_1_18_1","volume-title":"et al","author":"Hartstein A.","year":"2008","unstructured":"Hartstein , A. et al . 2008 . On the Nature of Cache Miss Behavior: Is It √2? J. Instruction-Level Parallelism 10. Hartstein, A. et al. 2008. On the Nature of Cache Miss Behavior: Is It √2? J. Instruction-Level Parallelism 10."},{"key":"e_1_3_2_1_19_1","unstructured":"CACTI\n  : http:\/\/www.hpl.hp.com\/research\/cacti\/  CACTI: http:\/\/www.hpl.hp.com\/research\/cacti\/"},{"key":"e_1_3_2_1_20_1","volume-title":"2010 update","author":"International","year":"2011","unstructured":"ITRS. International technology roadmap for semiconductors , 2010 update , 2011 . URL http:\/\/www.itrs.net ITRS. International technology roadmap for semiconductors, 2010 update, 2011. URL http:\/\/www.itrs.net"},{"key":"e_1_3_2_1_21_1","volume-title":"Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture.","author":"Keckler S.","year":"2011","unstructured":"Keckler , S. 2011 . Life After Dennard and How I Learned to Love the Picojoule . In Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture. Keckler, S. 2011. Life After Dennard and How I Learned to Love the Picojoule. In Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture."},{"key":"e_1_3_2_1_22_1","volume-title":"Low-Energy Data Cache Using Sign Compression and Cache Line Bisection. Second Annual workshop on Memory Performance Issues.","author":"Kim N.","unstructured":"Kim , N. et al. 2002 . Low-Energy Data Cache Using Sign Compression and Cache Line Bisection. Second Annual workshop on Memory Performance Issues. Kim, N. et al. 2002. Low-Energy Data Cache Using Sign Compression and Cache Line Bisection. Second Annual workshop on Memory Performance Issues."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155670"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1016\/S1383-7621(00)00030-8"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1147\/sj.71.0015"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"key":"e_1_3_2_1_28_1","volume-title":"et al","author":"Naffziger S.","year":"2002","unstructured":"Naffziger , S. et al . 2002 . Apparatus for cache compression engine for data compression of on-chip caches to increase effective cache size. US patent 6,640,283. Naffziger, S. et al. 2002. Apparatus for cache compression engine for data compression of on-chip caches to increase effective cache size. US patent 6,640,283."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370870"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305156"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/191995.192072"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.452.0271"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360150"},{"key":"e_1_3_2_1_34_1","volume-title":"Solid-State Circuits Conference Digest of Technical Papers.","author":"Weiss D.","unstructured":"Weiss , D. et al. 2011. An 8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing . Solid-State Circuits Conference Digest of Technical Papers. Weiss, D. et al. 2011. An 8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing. Solid-State Circuits Conference Digest of Technical Papers."},{"key":"e_1_3_2_1_35_1","volume-title":"Proceedings of the 35th Annual IEEE\/ACM International Symposium on Microarchitecture.","author":"Yang J.","unstructured":"Yang , J. et al. 2002. Energy Efficient Frequent Value Data Cache Design . In Proceedings of the 35th Annual IEEE\/ACM International Symposium on Microarchitecture. Yang, J. et al. 2002. Energy Efficient Frequent Value Data Cache Design. In Proceedings of the 35th Annual IEEE\/ACM International Symposium on Microarchitecture."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/581888.581894"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360154"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000100"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.5"}],"event":{"name":"MICRO-46: The 46th Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Davis California","acronym":"MICRO-46","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE CS"]},"container-title":["Proceedings of the 46th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2540708.2540715","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2540708.2540715","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:10:33Z","timestamp":1750234233000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2540708.2540715"}},"subtitle":["exploiting spatial locality for energy-optimized compressed caching"],"short-title":[],"issued":{"date-parts":[[2013,12,7]]},"references-count":38,"alternative-id":["10.1145\/2540708.2540715","10.1145\/2540708"],"URL":"https:\/\/doi.org\/10.1145\/2540708.2540715","relation":{},"subject":[],"published":{"date-parts":[[2013,12,7]]},"assertion":[{"value":"2013-12-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}