{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:46:41Z","timestamp":1772725601130,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":62,"publisher":"ACM","license":[{"start":{"date-parts":[[2013,12,7]],"date-time":"2013-12-07T00:00:00Z","timestamp":1386374400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["954107"],"award-info":[{"award-number":["954107"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2013,12,7]]},"DOI":"10.1145\/2540708.2540717","type":"proceedings-article","created":{"date-parts":[[2013,12,17]],"date-time":"2013-12-17T13:36:21Z","timestamp":1387287381000},"page":"86-98","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":96,"title":["A locality-aware memory hierarchy for energy-efficient GPU architectures"],"prefix":"10.1145","author":[{"given":"Minsoo","family":"Rhu","sequence":"first","affiliation":[{"name":"University of Texas at Austin, Austin, Texas"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Sullivan","sequence":"additional","affiliation":[{"name":"University of Texas at Austin, Austin, Texas"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jingwen","family":"Leng","sequence":"additional","affiliation":[{"name":"University of Texas at Austin, Austin, Texas"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mattan","family":"Erez","sequence":"additional","affiliation":[{"name":"University of Texas at Austin, Austin, Texas"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,12,7]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454152"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2012.6402918"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.12"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654082"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815992"},{"key":"e_1_3_2_1_7_1","volume-title":"February","author":"Fung W. W.","year":"2011","unstructured":"W. W. Fung and T. M. Aamodt , \" Thread Block Compaction for Efficient SIMT Control Flow,\" in 17th International Symposium on High Performance Computer Architecture (HPCA-17) , February 2011 . W. W. Fung and T. M. Aamodt, \"Thread Block Compaction for Efficient SIMT Control Flow,\" in 17th International Symposium on High Performance Computer Architecture (HPCA-17), February 2011."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155656"},{"key":"e_1_3_2_1_9_1","volume-title":"June","author":"Rhu M.","year":"2012","unstructured":"M. Rhu and M. Erez , \" CAPRI: Prediction of Compaction-Adequacy for Handling Control-Divergence in GPGPU Architectures,\" in 39th International Symposium on Computer Architecture (ISCA-39) , June 2012 . M. Rhu and M. Erez, \"CAPRI: Prediction of Compaction-Adequacy for Handling Control-Divergence in GPGPU Architectures,\" in 39th International Symposium on Computer Architecture (ISCA-39), June 2012."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.16"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522352"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451158"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485953"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485954"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485951"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.89"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000100"},{"key":"e_1_3_2_1_18_1","volume-title":"The dynamic granularity memory system,\" in 39th International Symposium on Computer Architecture (ISCA-39)","author":"Yoon D. H.","year":"2012","unstructured":"D. H. Yoon , M. Sullivan , M. K. Jeong , and M. Erez , \" The dynamic granularity memory system,\" in 39th International Symposium on Computer Architecture (ISCA-39) , 2012 . D. H. Yoon, M. Sullivan, M. K. Jeong, and M. Erez, \"The dynamic granularity memory system,\" in 39th International Symposium on Computer Architecture (ISCA-39), 2012."},{"key":"e_1_3_2_1_19_1","volume-title":"Fermi","author":"NVIDIA Corporation","year":"2009","unstructured":"NVIDIA Corporation , \"NVIDI A's Next Generation CUDA Compute Architecture : Fermi ,\" 2009 . NVIDIA Corporation, \"NVIDIA's Next Generation CUDA Compute Architecture: Fermi,\" 2009."},{"key":"e_1_3_2_1_20_1","volume-title":"NVIDIA GeForce GTX 680","author":"NVIDIA Corporation","year":"2012","unstructured":"NVIDIA Corporation , \"Whitepaper : NVIDIA GeForce GTX 680 ,\" 2012 . NVIDIA Corporation, \"Whitepaper: NVIDIA GeForce GTX 680,\" 2012."},{"key":"e_1_3_2_1_21_1","unstructured":"AMD Corporation \"AMD Radeon HD 6900M Series Specifications \" 2010.  AMD Corporation \"AMD Radeon HD 6900M Series Specifications \" 2010."},{"key":"e_1_3_2_1_22_1","unstructured":"NVIDIA Corporation \"NVIDIA CUDA Programming Guide \" 2011.  NVIDIA Corporation \"NVIDIA CUDA Programming Guide \" 2011."},{"key":"e_1_3_2_1_23_1","unstructured":"AMD Corporation \"ATI Stream Computing OpenCL Programming Guide \" August 2010.  AMD Corporation \"ATI Stream Computing OpenCL Programming Guide \" August 2010."},{"key":"e_1_3_2_1_24_1","unstructured":"1Gb (32Mx32) GDDR5 SGRAM H5GQ1H24AFR Hynix 2009. 1Gb (32Mx32) GDDR5 SGRAM H5GQ1H24AFR Hynix 2009."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654102"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2008.13"},{"key":"e_1_3_2_1_27_1","volume-title":"Mar.","author":"Ware F. A.","year":"2005","unstructured":"F. A. Ware and C. Hampel , \" Micro-threaded row and column operations in a DRAM core,\" in Proc. the first Workshop on Unique Chips and Systems (UCAS) , Mar. 2005 . F. A. Ware and C. Hampel, \"Micro-threaded row and column operations in a DRAM core,\" in Proc. the first Workshop on Unique Chips and Systems (UCAS), Mar. 2005."},{"key":"e_1_3_2_1_28_1","volume-title":"Improving power and data efficiency with threaded memory modules,\" in Proceedings of the International Conference on Computer Design (ICCD)","author":"Ware F. A.","year":"2006","unstructured":"F. A. Ware and C. Hampel , \" Improving power and data efficiency with threaded memory modules,\" in Proceedings of the International Conference on Computer Design (ICCD) , 2006 . F. A. Ware and C. Hampel, \"Improving power and data efficiency with threaded memory modules,\" in Proceedings of the International Conference on Computer Design (ICCD), 2006."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771792"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.36"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1147\/sj.71.0015"},{"key":"e_1_3_2_1_32_1","first-page":"1","volume-title":"Storage and Analysis (SC), 2012 International Conference for. IEEE","author":"Li S.","year":"2012","unstructured":"S. Li and et al., \"Mage: adaptive granularity and ecc for resilient and power efficient memory systems,\" in High Performance Computing, Networking , Storage and Analysis (SC), 2012 International Conference for. IEEE , 2012 , pp. 1 -- 11 . S. Li and et al., \"Mage: adaptive granularity and ecc for resilient and power efficient memory systems,\" in High Performance Computing, Networking, Storage and Analysis (SC), 2012 International Conference for. IEEE, 2012, pp. 1--11."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1362622.1362646"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/279358.279404"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10010"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2304576.2304582"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/362686.362692"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/90.851975"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.641938"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264210"},{"key":"e_1_3_2_1_41_1","volume-title":"April","author":"Bakhoda A.","year":"2009","unstructured":"A. Bakhoda , G. Yuan , W. Fung , H. Wong , and T. Aamodt , \" Analyzing CUDA workloads using a detailed GPU simulator,\" in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2009) , April 2009 . A. Bakhoda, G. Yuan, W. Fung, H. Wong, and T. Aamodt, \"Analyzing CUDA workloads using a detailed GPU simulator,\" in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2009), April 2009."},{"key":"e_1_3_2_1_42_1","unstructured":"\"GPGPU-Sim \" http:\/\/www.gpgpu-sim.org.  \"GPGPU-Sim \" http:\/\/www.gpgpu-sim.org."},{"key":"e_1_3_2_1_43_1","unstructured":"\"DrSim \" http:\/\/lph.ece.utexas.edu\/public\/DrSim.  \"DrSim \" http:\/\/lph.ece.utexas.edu\/public\/DrSim."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168944"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2085991"},{"key":"e_1_3_2_1_46_1","unstructured":"\"GPGPU-Sim Manual \" http:\/\/www.gpgpu-sim.org\/manual.  \"GPGPU-Sim Manual \" http:\/\/www.gpgpu-sim.org\/manual."},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485964"},{"key":"e_1_3_2_1_48_1","unstructured":"NVIDIA Corporation \"CUDA C\/C++ SDK CODE Samples \" 2011.  NVIDIA Corporation \"CUDA C\/C++ SDK CODE Samples \" 2011."},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1186\/1471-2105-8-474"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000093"},{"key":"e_1_3_2_1_51_1","unstructured":"HMC \"Hybrid memory cube specification 1.0 \" Hybrid Memory Cube Consortium 2013.  HMC \"Hybrid memory cube specification 1.0 \" Hybrid Memory Cube Consortium 2013."},{"key":"e_1_3_2_1_52_1","volume-title":"Inc.","year":"2011","unstructured":"Hynix, \"Blazing a trail to high performance graphics,\" Hynix Semiconductor , Inc. , 2011 . Hynix, \"Blazing a trail to high performance graphics,\" Hynix Semiconductor, Inc., 2011."},{"key":"e_1_3_2_1_53_1","unstructured":"JEDEC \"JESD 229 Wide I\/O SDR \" 2011.  JEDEC \"JESD 229 Wide I\/O SDR \" 2011."},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736064"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/191995.192072"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305156"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/224538.224622"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/1142473.1142477"},{"key":"e_1_3_2_1_59_1","unstructured":"\"bcache: A Linux kernel block layer cache \" http:\/\/bcache.evilpiepirate.org\/.  \"bcache: A Linux kernel block layer cache \" http:\/\/bcache.evilpiepirate.org\/."},{"key":"e_1_3_2_1_60_1","first-page":"2196","volume-title":"Twenty-third AnnualJoint Conference of the IEEE Computer and Communications Societies","volume":"4","author":"Chang F.","year":"2004","unstructured":"F. Chang , W.-c. Feng , and K. Li , \" Approximate caches for packet classification,\" in INFOCOM 2004 . Twenty-third AnnualJoint Conference of the IEEE Computer and Communications Societies , vol. 4 . IEEE, 2004 , pp. 2196 -- 2207 . F. Chang, W.-c. Feng, and K. Li, \"Approximate caches for packet classification,\" in INFOCOM 2004. Twenty-third AnnualJoint Conference of the IEEE Computer and Communications Societies, vol. 4. IEEE, 2004, pp. 2196--2207."},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICDE.2013.6544902"},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/TKDE.2009.136"}],"event":{"name":"MICRO-46: The 46th Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Davis California","acronym":"MICRO-46","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE CS"]},"container-title":["Proceedings of the 46th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2540708.2540717","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2540708.2540717","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:10:33Z","timestamp":1750234233000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2540708.2540717"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12,7]]},"references-count":62,"alternative-id":["10.1145\/2540708.2540717","10.1145\/2540708"],"URL":"https:\/\/doi.org\/10.1145\/2540708.2540717","relation":{},"subject":[],"published":{"date-parts":[[2013,12,7]]},"assertion":[{"value":"2013-12-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}