{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,6]],"date-time":"2026-01-06T13:53:53Z","timestamp":1767707633660,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":33,"publisher":"ACM","license":[{"start":{"date-parts":[[2013,12,7]],"date-time":"2013-12-07T00:00:00Z","timestamp":1386374400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Spanish Gov.","award":["Consolider CSD2007-00050"],"award-info":[{"award-number":["Consolider CSD2007-00050"]}]},{"DOI":"10.13039\/501100004963","name":"Seventh Framework Programme","doi-asserted-by":"publisher","award":["HiPEAC-2 NoE"],"award-info":[{"award-number":["HiPEAC-2 NoE"]}],"id":[{"id":"10.13039\/501100004963","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Aragon Gov. and European ES"},{"name":"Spanish Gov. and European ERDF","award":["TIN2010-21291-C02-01, TIN2012-34557"],"award-info":[{"award-number":["TIN2010-21291-C02-01, TIN2012-34557"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2013,12,7]]},"DOI":"10.1145\/2540708.2540735","type":"proceedings-article","created":{"date-parts":[[2013,12,17]],"date-time":"2013-12-17T13:36:21Z","timestamp":1387287381000},"page":"310-321","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":34,"title":["The reuse cache"],"prefix":"10.1145","author":[{"given":"Jorge","family":"Albericio","sequence":"first","affiliation":[{"name":"University of Toronto"}]},{"given":"Pablo","family":"Ib\u00e1\u00f1ez","sequence":"additional","affiliation":[{"name":"University of Zaragoza"}]},{"given":"V\u00edctor","family":"Vi\u00f1als","sequence":"additional","affiliation":[{"name":"University of Zaragoza"}]},{"given":"Jos\u00e9 M.","family":"Llaber\u00eda","sequence":"additional","affiliation":[{"name":"UPC Barcelona Tech"}]}],"member":"320","published-online":{"date-parts":[[2013,12,7]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2400682.2400697"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/52400.52409"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168917.1168892"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370860"},{"key":"e_1_3_2_1_6_1","first-page":"55","volume-title":"Proc. of the 36th annual IEEE\/ACM Int. Symp. on Microarchitecture, MICRO 36","author":"Chishti Z.","unstructured":"Z. Chishti , M. D. Powell , and T. N. Vijaykumar . Distance associativity for high-performance energy-efficient non-uniform cache architectures . In Proc. of the 36th annual IEEE\/ACM Int. Symp. on Microarchitecture, MICRO 36 , pages 55 --, Washington, DC, USA, 2003. IEEE Computer Society. Z. Chishti, M. D. Powell, and T. N. Vijaykumar. Distance associativity for high-performance energy-efficient non-uniform cache architectures. In Proc. of the 36th annual IEEE\/ACM Int. Symp. on Microarchitecture, MICRO 36, pages 55--, Washington, DC, USA, 2003. IEEE Computer Society."},{"key":"e_1_3_2_1_8_1","volume-title":"Parallel Computer Architecture: A Hardware\/Software Approach. Morgan Kaufmann","author":"Culler D.","year":"1998","unstructured":"D. Culler , J. Singh , and A. Gupta . Parallel Computer Architecture: A Hardware\/Software Approach. Morgan Kaufmann , 1 st edition, 1998 . The Morgan Kaufmann Series in Computer Architecture and Design. D. Culler, J. Singh, and A. Gupta. Parallel Computer Architecture: A Hardware\/Software Approach. Morgan Kaufmann, 1st edition, 1998. The Morgan Kaufmann Series in Computer Architecture and Design.","edition":"1"},{"key":"e_1_3_2_1_9_1","volume-title":"Proc. of the 1st JILP Workshop on Computer Architecture Competitions","author":"Gao H.","year":"2010","unstructured":"H. Gao and C. Wilkerson . A dueling segmented lru replacement algorithm with adaptive bypassing . In Proc. of the 1st JILP Workshop on Computer Architecture Competitions , 2010 . H. Gao and C. Wilkerson. A dueling segmented lru replacement algorithm with adaptive bypassing. In Proc. of the 1st JILP Workshop on Computer Architecture Competitions, 2010."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.52"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454145"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.268884"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379268"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169030"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.24"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379259"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370862"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771793"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-32820-6_22"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/2337159.2337217"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"key":"e_1_3_2_1_24_1","unstructured":"S. Microsystems. UltraSPARC T2 supplement to the UltraSPARC architecture 2007. Draft D1.4.3 19 Sep 2007.  S. Microsystems. UltraSPARC T2 supplement to the UltraSPARC architecture 2007. Draft D1.4.3 19 Sep 2007 ."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.30"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.52"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305156"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370868"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/191995.192072"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346185"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.223990"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155671"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155672"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1787275.1787314"}],"event":{"name":"MICRO-46: The 46th Annual IEEE\/ACM International Symposium on Microarchitecture","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE CS"],"location":"Davis California","acronym":"MICRO-46"},"container-title":["Proceedings of the 46th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2540708.2540735","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2540708.2540735","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:10:23Z","timestamp":1750234223000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2540708.2540735"}},"subtitle":["downsizing the shared last-level cache"],"short-title":[],"issued":{"date-parts":[[2013,12,7]]},"references-count":33,"alternative-id":["10.1145\/2540708.2540735","10.1145\/2540708"],"URL":"https:\/\/doi.org\/10.1145\/2540708.2540735","relation":{},"subject":[],"published":{"date-parts":[[2013,12,7]]},"assertion":[{"value":"2013-12-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}