{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:20:53Z","timestamp":1750306853321,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":33,"publisher":"ACM","license":[{"start":{"date-parts":[[2013,12,7]],"date-time":"2013-12-07T00:00:00Z","timestamp":1386374400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2013,12,7]]},"DOI":"10.1145\/2540708.2540739","type":"proceedings-article","created":{"date-parts":[[2013,12,17]],"date-time":"2013-12-17T13:36:21Z","timestamp":1387287381000},"page":"359-370","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":39,"title":["Multi-grain coherence directories"],"prefix":"10.1145","author":[{"given":"Jason","family":"Zebchuk","sequence":"first","affiliation":[{"name":"University of Toronto"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Babak","family":"Falsafi","sequence":"additional","affiliation":[{"name":"EcoCloud, EPFL"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Moshovos","sequence":"additional","affiliation":[{"name":"University of Toronto"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2013,12,7]]},"reference":[{"volume-title":"White Paper","year":"2008","key":"e_1_3_2_1_1_1","unstructured":"First the tick , now the tock: Next generation Intel microarchitecture (Nehalem) . White Paper , 2008 . First the tick, now the tock: Next generation Intel microarchitecture (Nehalem). White Paper, 2008."},{"key":"e_1_3_2_1_2_1","unstructured":"OpenSPARC#8482; system-on-chip (SoC) microarchitecture specification May 2008.  OpenSPARC #8482; system-on-chip (SoC) microarchitecture specification May 2008."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/52400.52432"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.39"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339696"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.31"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/800105.803400"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/645608.662005"},{"key":"e_1_3_2_1_10_1","volume-title":"Hot Chips 24","author":"Chrysos G.","year":"2012","unstructured":"G. Chrysos . Intel\u00ae many integrated core architecture: The first Intel\u00ae Xeon Phi coprocessor (codenamed Knights Corner) . presented at Hot Chips 24 , Stanford, CA , Aug. 2012 . G. Chrysos. Intel\u00ae many integrated core architecture: The first Intel\u00ae Xeon Phi coprocessor (codenamed Knights Corner). presented at Hot Chips 24, Stanford, CA, Aug. 2012."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000076"},{"key":"e_1_3_2_1_12_1","volume-title":"Proc. of the Int'l Symposium on High Performance Computer Architecture","author":"Ferdman M.","year":"2011","unstructured":"M. Ferdman : A scalable directory for many-core systems . In Proc. of the Int'l Symposium on High Performance Computer Architecture , Feb. 2011 . M. Ferdman et al. Cuckoo directory: A scalable directory for many-core systems. In Proc. of the Int'l Symposium on High Performance Computer Architecture, Feb. 2011."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"e_1_3_2_1_14_1","volume-title":"Hot Chips 18","author":"Grohoski G.","year":"2006","unstructured":"G. Grohoski . Niagara2 : A highly-threaded server-on-a-chip . presented at Hot Chips 18 , Stanford, CA , Aug. 2006 . G. Grohoski. Niagara2: A highly-threaded server-on-a-chip. presented at Hot Chips 18, Stanford, CA, Aug. 2006."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-010-9321-5"},{"key":"e_1_3_2_1_16_1","volume-title":"Proc. of the Int'l Conf. on Parallel Processing","author":"Gupta A.","year":"1990","unstructured":"A. Gupta , W.-D. Weber , and T. Mowry . Reducing memory and traffic requirements for scalable directory-based cache coherence schemes . In Proc. of the Int'l Conf. on Parallel Processing , 1990 . A. Gupta, W.-D. Weber, and T. Mowry. Reducing memory and traffic requirements for scalable directory-based cache coherence schemes. In Proc. of the Int'l Conf. on Parallel Processing, 1990."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555779"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264206"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2209249.2209269"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.42"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370853"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.20"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168950"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165152"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2012.7476504"},{"key":"e_1_3_2_1_27_1","volume-title":"USA","author":"Wallach D. A.","year":"1992","unstructured":"D. A. Wallach . PHD : A hierarchical cache coherent protocol. Technical report, Cambridge, MA , USA , 1992 . D. A. Wallach. PHD: A hierarchical cache coherent protocol. Technical report, Cambridge, MA, USA, 1992."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.79"},{"issue":"7","key":"e_1_3_2_1_29_1","first-page":"13","article-title":"Tilera sees opening in clouds","volume":"25","author":"Wheeler B.","year":"2011","unstructured":"B. Wheeler . Tilera sees opening in clouds . Microprocessor Report , 25 ( 7 ): 13 -- 16 , July 2011 . B. Wheeler. Tilera sees opening in clouds. Microprocessor Report, 25(7):13--16, July 2011.","journal-title":"Microprocessor Report"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859629"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.139202"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669166"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854294"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.10"}],"event":{"name":"MICRO-46: The 46th Annual IEEE\/ACM International Symposium on Microarchitecture","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE CS"],"location":"Davis California","acronym":"MICRO-46"},"container-title":["Proceedings of the 46th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2540708.2540739","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2540708.2540739","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:10:23Z","timestamp":1750234223000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2540708.2540739"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12,7]]},"references-count":33,"alternative-id":["10.1145\/2540708.2540739","10.1145\/2540708"],"URL":"https:\/\/doi.org\/10.1145\/2540708.2540739","relation":{},"subject":[],"published":{"date-parts":[[2013,12,7]]},"assertion":[{"value":"2013-12-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}