{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,6]],"date-time":"2025-11-06T11:39:50Z","timestamp":1762429190537,"version":"3.41.0"},"reference-count":32,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2013,12,1]],"date-time":"2013-12-01T00:00:00Z","timestamp":1385856000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100004926","name":"Texas Higher Education Coordinating Board","doi-asserted-by":"publisher","award":["010115-0079-2009"],"award-info":[{"award-number":["010115-0079-2009"]}],"id":[{"id":"10.13039\/100004926","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF-1162215"],"award-info":[{"award-number":["CCF-1162215"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2013,12]]},"abstract":"<jats:p>\n            Inclusive caches have been widely used in Chip Multiprocessors (CMPs) to simplify cache coherence. However, they have poor performance compared with noninclusive caches not only because of the limited capacity of the entire cache hierarchy but also due to ignorance of temporal locality of the Last-Level Cache (LLC). Blocks that are highly referenced (referred to as\n            <jats:italic>hot blocks<\/jats:italic>\n            ) are always hit in higher-level caches (e.g., L1 cache) and are rarely referenced in the LLC. Therefore, they become replacement victims in the LLC. Due to the inclusion property, blocks evicted from the LLC have to also be invalidated from higher-level caches. Invalidation of hot blocks from the entire cache hierarchy introduces costly off-chip misses that makes the inclusive cache perform poorly.\n          <\/jats:p>\n          <jats:p>\n            Neither blocks that are highly referenced in the LLC nor blocks that are highly referenced in higher-level caches should be the LLC replacement victims. We propose\n            <jats:italic>temporal-based multilevel correlating cache replacement<\/jats:italic>\n            for inclusive caches to evict blocks in the LLC that are also not hot in higher-level caches using correlated temporal information acquired from all levels of a cache hierarchy with minimal overhead. Invalidation of these blocks does not hurt the performance. By contrast, replacing them as early as possible with useful blocks helps improve cache performance. Based on our experiments, in a dual-core CMP, an inclusive cache with temporal-based multilevel correlating cache replacement significantly outperforms an inclusive cache with traditional LRU replacement by yielding an average speedup of 12.7%, which is comparable to an enhanced noninclusive cache, while requiring less than 1% of storage overhead.\n          <\/jats:p>","DOI":"10.1145\/2541228.2555290","type":"journal-article","created":{"date-parts":[[2014,1,14]],"date-time":"2014-01-14T13:39:57Z","timestamp":1389706797000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Temporal-based multilevel correlating inclusive cache replacement"],"prefix":"10.1145","volume":"10","author":[{"given":"Yingying","family":"Tian","sequence":"first","affiliation":[{"name":"Texas A&amp;M University, AMD"}]},{"given":"Samira M.","family":"Khan","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Intel"}]},{"given":"Daniel A.","family":"Jim\u00e9nez","sequence":"additional","affiliation":[{"name":"Texas A&amp;M University"}]}],"member":"320","published-online":{"date-parts":[[2013,12]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Retrieved","author":"AMD.","year":"2012","unstructured":"AMD. 2012 . AMD FX processors. (2012) . Retrieved November 13, 2013, from http:\/\/www.amd.com\/us\/products\/desktop\/processors\/amdfx\/. AMD. 2012. AMD FX processors. (2012). Retrieved November 13, 2013, from http:\/\/www.amd.com\/us\/products\/desktop\/processors\/amdfx\/."},{"doi-asserted-by":"publisher","key":"e_1_2_1_2_1","DOI":"10.1145\/633625.52409"},{"volume-title":"Intel Core i7-800 processor series and the Intel Core i5-700 processor series based on Intel microarchitecture (Nehalem). White paper","author":"Casazza J.","unstructured":"Casazza , J. 2009. Intel Core i7-800 processor series and the Intel Core i5-700 processor series based on Intel microarchitecture (Nehalem). White paper , Intel Corp . Casazza, J. 2009. Intel Core i7-800 processor series and the Intel Core i5-700 processor series based on Intel microarchitecture (Nehalem). White paper, Intel Corp.","key":"e_1_2_1_3_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_4_1","DOI":"10.1109\/FMCAD.2006.28"},{"doi-asserted-by":"publisher","key":"e_1_2_1_5_1","DOI":"10.1145\/339647.339669"},{"doi-asserted-by":"publisher","key":"e_1_2_1_6_1","DOI":"10.1145\/379240.379259"},{"volume-title":"Proceedings of the 7th Workshop on Duplicating, Deconstructing, and Debunking (WDDD'08)","author":"Garde R. V.","unstructured":"Garde , R. V. , Subramaniam , S. , and Loh , G. H . 2008. Deconstructing the inefficacy of global cache replacement policies . In Proceedings of the 7th Workshop on Duplicating, Deconstructing, and Debunking (WDDD'08) . Garde, R. V., Subramaniam, S., and Loh, G. H. 2008. Deconstructing the inefficacy of global cache replacement policies. In Proceedings of the 7th Workshop on Duplicating, Deconstructing, and Debunking (WDDD'08).","key":"e_1_2_1_7_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_8_1","DOI":"10.1145\/2000064.2000075"},{"doi-asserted-by":"publisher","key":"e_1_2_1_9_1","DOI":"10.1145\/1186736.1186737"},{"volume-title":"Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA'02)","author":"Hu Z.","unstructured":"Hu , Z. , Kaxiras , S. , and Martonosi , M . 2002. Timekeeping in the memory system: Predicting and optimizing memory behavior . In Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA'02) . IEEE, Los Alamitos, CA, 209--220. http:\/\/dl.acm.org\/citation.cfm&quest;id=545215.545239. Hu, Z., Kaxiras, S., and Martonosi, M. 2002. Timekeeping in the memory system: Predicting and optimizing memory behavior. In Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA'02). IEEE, Los Alamitos, CA, 209--220. http:\/\/dl.acm.org\/citation.cfm&quest;id=545215.545239.","key":"e_1_2_1_10_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_11_1","DOI":"10.1109\/MICRO.2010.52"},{"doi-asserted-by":"publisher","key":"e_1_2_1_12_1","DOI":"10.1145\/192007.192015"},{"doi-asserted-by":"publisher","key":"e_1_2_1_13_1","DOI":"10.1145\/1854273.1854333"},{"doi-asserted-by":"publisher","key":"e_1_2_1_14_1","DOI":"10.1109\/MICRO.2010.24"},{"doi-asserted-by":"publisher","key":"e_1_2_1_15_1","DOI":"10.1109\/TC.2007.70816"},{"volume-title":"Proceedings of the 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC'10)","author":"Kurd N. A.","unstructured":"Kurd , N. A. , Bhamidipati , S. , Mozak , C. , Miller , J. L. , Wilson , T. M. , Nemani , M. , and Chowdhury , M . 2010. Westmere: A family of 32nm IA processors . In Proceedings of the 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC'10) . IEEE, Los Alamitos, CA, 96--97. Kurd, N. A., Bhamidipati, S., Mozak, C., Miller, J. L., Wilson, T. M., Nemani, M., and Chowdhury, M. 2010. Westmere: A family of 32nm IA processors. In Proceedings of the 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC'10). IEEE, Los Alamitos, CA, 96--97.","key":"e_1_2_1_16_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_17_1","DOI":"10.1145\/223982.223995"},{"doi-asserted-by":"publisher","key":"e_1_2_1_18_1","DOI":"10.1145\/384286.264211"},{"unstructured":"Muralimanohar N. Balasubramonian R. and Jouppi N. P. 2009. CACTI 6.0: A tool to model large caches. Technical report HPL-2009-85. HP Laboratories.  Muralimanohar N. Balasubramonian R. and Jouppi N. P. 2009. CACTI 6.0: A tool to model large caches. Technical report HPL-2009-85. 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Cache replacement policy revisited . In Proceedings of the 6th Workshop on Duplicating, Deconstructing, and Debunking (ISCA). Zahran, M. 2007. Cache replacement policy revisited. In Proceedings of the 6th Workshop on Duplicating, Deconstructing, and Debunking (ISCA)."},{"key":"e_1_2_1_30_1","first-page":"2","article-title":"Non-inclusion property in multi-level caches revisited","volume":"14","author":"Zahran M.","year":"2007","unstructured":"Zahran , M. , Albayraktaroglu , K. , and Franklin , M. 2007 . Non-inclusion property in multi-level caches revisited . Int. J. Comput. Appl. 14 , 2 , 99. Zahran, M., Albayraktaroglu, K., and Franklin, M. 2007. Non-inclusion property in multi-level caches revisited. Int. J. Comput. Appl. 14, 2, 99.","journal-title":"Int. J. Comput. Appl."},{"doi-asserted-by":"publisher","key":"e_1_2_1_31_1","DOI":"10.1145\/1787275.1787315"},{"volume-title":"Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software. 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