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Code Optim."],"published-print":{"date-parts":[[2013,12]]},"abstract":"<jats:p>The design process of a microprocessor requires representative workloads to steer the search process toward an optimum design point for the target application domain. However, considering a broad set of workloads to cover the large space of potential workloads is infeasible given how time-consuming design space exploration typically is. Hence, it is crucial to select a small yet representative set of workloads, which leads to a shorter design cycle while yielding a (near) optimal design.<\/jats:p>\n          <jats:p>\n            Prior work has mostly looked into selecting representative benchmarks; however, limited attention was given to the selection of benchmark\n            <jats:italic>inputs<\/jats:italic>\n            and how this affects workload representativeness during design space exploration. Using a set of 1,000 inputs for a number of embedded benchmarks and a design space with around 1,700 design points, we find that selecting a single or three random input(s) per benchmark potentially (in a worst-case scenario) leads to a suboptimal design that is 56% and 33% off, on average, relative to the optimal design in our design space in terms of Energy-Delay Product (EDP). We then propose and evaluate a number of methods for selecting representative inputs and show that we can find the optimum design point with as few as three inputs.\n          <\/jats:p>","DOI":"10.1145\/2541228.2555294","type":"journal-article","created":{"date-parts":[[2014,1,14]],"date-time":"2014-01-14T13:39:57Z","timestamp":1389706797000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Selecting representative benchmark inputs for exploring microprocessor design spaces"],"prefix":"10.1145","volume":"10","author":[{"given":"Maximilien B.","family":"Breughe","sequence":"first","affiliation":[{"name":"Ghent University, Gent, Belgium"}]},{"given":"Lieven","family":"Eeckhout","sequence":"additional","affiliation":[{"name":"Ghent University, Gent, Belgium"}]}],"member":"320","published-online":{"date-parts":[[2013,12]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1167473.1167488"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2012.6189202"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2011.5941070"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1806596.1806647"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"volume-title":"Proceedings of the 2005 IEEE International Symposium on Workload Characterization (IISWC'05)","author":"Eeckhout L.","key":"e_1_2_1_9_1","unstructured":"Eeckhout , L. , Sampson , J. , and Calder , B . 2005. Exploiting program microarchitecture independent characteristics and phase behavior for reduced benchmark suite simulation . In Proceedings of the 2005 IEEE International Symposium on Workload Characterization (IISWC'05) . 2--12. Eeckhout, L., Sampson, J., and Calder, B. 2005. Exploiting program microarchitecture independent characteristics and phase behavior for reduced benchmark suite simulation. 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Basic block distribution analysis to find periodic behavior and simulation points in applications . In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'01) . 3--14. Sherwood, T., Perelman, E., and Calder, B. 2001. Basic block distribution analysis to find periodic behavior and simulation points in applications. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'01). 3--14."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"volume-title":"Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS'06)","author":"Van Biesbrouck M.","key":"e_1_2_1_31_1","unstructured":"Van Biesbrouck , M. , Eeckhout , L. , and Calder , B . 2006. Considering all starting points for simultaneous multithreading simulation . In Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS'06) . 143--153. Van Biesbrouck, M., Eeckhout, L., and Calder, B. 2006. Considering all starting points for simultaneous multithreading simulation. In Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS'06). 143--153."},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2007.4362195"},{"volume-title":"Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS'04)","author":"Van Biesbrouck M.","key":"e_1_2_1_33_1","unstructured":"Van Biesbrouck , M. , Sherwood , T. , and Calder , B . 2004. A co-phase matrix to guide simultaneous multithreading simulation . In Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS'04) . 45--56. Van Biesbrouck, M., Sherwood, T., and Calder, B. 2004. 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