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Archit. Code Optim."],"published-print":{"date-parts":[[2013,12]]},"abstract":"<jats:p>The simplicity of requester-wins Hardware Transactional Memory (HTM) makes it easy to incorporate in existing chip multiprocessors. Hence, such systems are expected to be widely available in the near future. Unfortunately, these implementations are prone to suffer severe performance degradation due to transient and persistent livelock conditions. This article shows that existing techniques are unable to mitigate this degradation effectively. It then proposes and evaluates four novel techniques\u2014two software-based that employ information provided by the hardware and two that require simple core-local hardware additions\u2014which have the potential to boost the performance of requester-wins HTM designs substantially.<\/jats:p>","DOI":"10.1145\/2541228.2555299","type":"journal-article","created":{"date-parts":[[2014,1,14]],"date-time":"2014-01-14T13:39:57Z","timestamp":1389706797000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Techniques to improve performance in requester-wins hardware transactional memory"],"prefix":"10.1145","volume":"10","author":[{"given":"Adri\u00e0","family":"Armejach","sequence":"first","affiliation":[{"name":"Barcelona Supercomputing Center, Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"}]},{"given":"Ruben","family":"Titos-Gil","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology, Gothenburg, Sweden"}]},{"given":"Anurag","family":"Negi","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology, Gothenburg, Sweden"}]},{"given":"Osman S.","family":"Unsal","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"given":"Adri\u00e1n","family":"Cristal","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Universitat Polit\u00e8cnica de Catalunya, IIIA - Artificial Intelligence Research Institute (CSIC), Barcelona, Spain"}]}],"member":"320","published-online":{"date-parts":[[2013,12]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.41"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669133"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/362686.362692"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815995"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250674"},{"volume-title":"Proceedings of the IEEE International Symposium on Workload Characterization.","author":"Cao Minh C.","key":"e_1_2_1_7_1","unstructured":"Cao Minh , C. , Chung , J. , Kozyrakis , C. , and Olukotun , K . 2008. STAMP: Stanford transactional applications for multi-processing . In Proceedings of the IEEE International Symposium on Workload Characterization. Cao Minh, C., Chung, J., Kozyrakis, C., and Olukotun, K. 2008. STAMP: Stanford transactional applications for multi-processing. In Proceedings of the IEEE International Symposium on Workload Characterization."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1755913.1755918"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.40"},{"key":"e_1_2_1_10_1","volume-title":"Bay Area Workshop on Transactional Memory.","author":"Click C.","year":"2009","unstructured":"Click , C. 2009 . Azul\u2019s experiences with hardware transactional memory. HP Labs , Bay Area Workshop on Transactional Memory. Click, C. 2009. Azul\u2019s experiences with hardware transactional memory. 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D., Hertzberg, B., Prabhu, M. K., Wijaya, H., Kozyrakis, C., and Olukotun, K. 2004. Transactional memory coherence and consistency. In Proceedings of the 31st International Symposium on Computer Architecture."},{"key":"e_1_2_1_17_1","doi-asserted-by":"crossref","unstructured":"Harris T. Larus J. and Rajwar R. 2010. Transactional Memory 2nd Ed. Morgan and Claypool Publishers.   Harris T. Larus J. and Rajwar R. 2010. Transactional Memory 2nd Ed. Morgan and Claypool Publishers.","DOI":"10.1007\/978-3-031-01728-5"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165164"},{"key":"e_1_2_1_19_1","unstructured":"Intel Corporation. 2012. Transaction Synchronization Extensions (TSX). In Intel Architecture Instruction Set Extensions Programming Reference. 506--529. Retrieved from http:\/\/software.intel.com\/file\/41604.  Intel Corporation. 2012. Transaction Synchronization Extensions (TSX). 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