{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T14:53:42Z","timestamp":1761663222040,"version":"3.41.0"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2013,12,1]],"date-time":"2013-12-01T00:00:00Z","timestamp":1385856000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF-0702452"],"award-info":[{"award-number":["CCF-0702452"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2013,12]]},"abstract":"<jats:p>Spin-Transfer Torque RAM (STT-RAM), a promising alternative to SRAM for reducing leakage power consumption, has been widely studied to mitigate the impact of its asymmetrically long write latency. Recently, STT-RAM has been proposed for L1 caches by relaxing the data retention time to improve write performance and dynamic energy. However, as the technology scales down from 65nm to 22nm, the performance of the read operation scales poorly due to reduced sense margins and sense amplifier delays. In this article, we leverage a dual-mode STT memory cell to design a configurable L1 cache architecture termed C1C to mitigate read performance barriers with technology scaling. Guided by application access characteristics discovered through novel compiler analyses, the proposed cache adaptively switches between a high performance and a low-power access mode. Our evaluation demonstrates that the proposed cache with compiler guidance outperforms a state-of-the-art STT-RAM cache design by 9% with high dynamic energy efficiency, leading to significant performance\/watt improvements over several competing approaches.<\/jats:p>","DOI":"10.1145\/2541228.2555308","type":"journal-article","created":{"date-parts":[[2014,1,14]],"date-time":"2014-01-14T13:39:57Z","timestamp":1389706797000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["C1C"],"prefix":"10.1145","volume":"10","author":[{"given":"Yong","family":"Li","sequence":"first","affiliation":[{"name":"University of Pittsburgh, PA, USA"}]},{"given":"Yaojun","family":"Zhang","sequence":"additional","affiliation":[{"name":"University of Pittsburgh, PA, USA"}]},{"given":"Hai","family":"LI","sequence":"additional","affiliation":[{"name":"University of Pittsburgh, PA, USA"}]},{"given":"Yiran","family":"Chen","sequence":"additional","affiliation":[{"name":"University of Pittsburgh, PA, USA"}]},{"given":"Alex K.","family":"Jones","sequence":"additional","affiliation":[{"name":"University of Pittsburgh, PA, USA"}]}],"member":"320","published-online":{"date-parts":[[2013,12]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Compilers: Principles, Techniques, and Tools","author":"Aho A. V.","year":"2006","unstructured":"Aho , A. V. , Lam , M. S. , Sethi , R. , and Ullman , J. D . 2006 . Compilers: Principles, Techniques, and Tools , 2 nd ed. Addison Wesley . Aho, A. V., Lam, M. S., Sethi, R., and Ullman, J. D. 2006. Compilers: Principles, Techniques, and Tools, 2nd ed. Addison Wesley.","edition":"2"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/140901.141896"},{"key":"e_1_2_1_3_1","volume-title":"Technical Report TR-811-08. Princeton University.","author":"Bienia C.","year":"2008","unstructured":"Bienia , C. , Kumar , S. , Singh , J. P. , and Li , K . 2008 . The PARSEC Benchmark Suite: Characterization and Architectural Implications . Technical Report TR-811-08. Princeton University. Bienia, C., Kumar, S., Singh, J. P., and Li, K. 2008. The PARSEC Benchmark Suite: Characterization and Architectural Implications. Technical Report TR-811-08. Princeton University."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840847"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333717"},{"volume-title":"Proceedings of the International Midwest Symposium on Circuits and Systems (MWSCAS\u201910)","author":"Cheng C.-T.","key":"e_1_2_1_6_1","unstructured":"Cheng , C.-T. , Tsai , Y.-C. , and Cheng , K . -H. 2010. A high-speed current mode sense amplifier for Spin-Torque Transfer Magnetic Random Access Memory . In Proceedings of the International Midwest Symposium on Circuits and Systems (MWSCAS\u201910) . 181--184. Cheng, C.-T., Tsai, Y.-C., and Cheng, K.-H. 2010. A high-speed current mode sense amplifier for Spin-Torque Transfer Magnetic Random Access Memory. In Proceedings of the International Midwest Symposium on Circuits and Systems (MWSCAS\u201910). 181--184."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1088\/0953-8984\/19\/16\/165209"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/781131.781159"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816012"},{"volume-title":"Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201905)","author":"Hosomi M.","key":"e_1_2_1_10_1","unstructured":"Hosomi , M. and others. 2005a. A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM . In Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201905) . Hosomi, M. and others. 2005a. A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM. In Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201905)."},{"key":"e_1_2_1_11_1","first-page":"459","article-title":"A novel nonvolatile memory with spin torque transfer magnetization switching","volume":"2","author":"Hosomi M.","year":"2005","unstructured":"Hosomi , M. , Yamagishi , H. , Yamamoto , T. , Bessha , K. and others. 2005 b. A novel nonvolatile memory with spin torque transfer magnetization switching : Spin-RAM. IEDM Technical Digest 2 , 25, 459 -- 462 . Hosomi, M., Yamagishi, H., Yamamoto, T., Bessha, K. and others. 2005b. A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM. IEDM Technical Digest 2, 25, 459--462.","journal-title":"Spin-RAM. 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