{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,5]],"date-time":"2026-02-05T12:38:16Z","timestamp":1770295096848,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":13,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,2,26]]},"DOI":"10.1145\/2554688.2554762","type":"proceedings-article","created":{"date-parts":[[2014,2,18]],"date-time":"2014-02-18T09:10:41Z","timestamp":1392714641000},"page":"147-150","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A FPGA prototype design emphasis on low power technique"],"prefix":"10.1145","author":[{"given":"Xu","family":"Hanyang","sequence":"first","affiliation":[{"name":"Fudan University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wang","family":"Jian","sequence":"additional","affiliation":[{"name":"Fudan University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jin","family":"Meilai","sequence":"additional","affiliation":[{"name":"Fudan University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,2,26]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2011 International Technology Roadmap for Semiconductors (ITRS).  2011 International Technology Roadmap for Semiconductors (ITRS)."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065653"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1561\/1000000005"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968285"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968288"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435280"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508135"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCO.2013.6481152"},{"key":"e_1_3_2_1_11_1","volume-title":"International Conference on Signal Processing and Communications (SPCOM), 1--5.","author":"Sreenivaas V. L.","year":"2010"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2392616.2392618"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2003.1249359"}],"event":{"name":"FPGA'14: The 2014 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","location":"Monterey California USA","acronym":"FPGA'14","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2014 ACM\/SIGDA international symposium on Field-programmable gate arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2554688.2554762","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,10]],"date-time":"2023-01-10T07:43:46Z","timestamp":1673336626000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2554688.2554762"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2,26]]},"references-count":13,"alternative-id":["10.1145\/2554688.2554762","10.1145\/2554688"],"URL":"https:\/\/doi.org\/10.1145\/2554688.2554762","relation":{},"subject":[],"published":{"date-parts":[[2014,2,26]]},"assertion":[{"value":"2014-02-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}