{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,27]],"date-time":"2025-09-27T13:58:22Z","timestamp":1758981502984},"publisher-location":"New York, NY, USA","reference-count":31,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,2,26]]},"DOI":"10.1145\/2554688.2554779","type":"proceedings-article","created":{"date-parts":[[2014,2,18]],"date-time":"2014-02-18T09:10:41Z","timestamp":1392714641000},"page":"99-108","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Square-rich fixed point polynomial evaluation on FPGAs"],"prefix":"10.1145","author":[{"given":"Simin","family":"Xu","sequence":"first","affiliation":[{"name":"Xilinx Asia Pacific, Singapore, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Suhaib A.","family":"Fahmy","sequence":"additional","affiliation":[{"name":"Nanyang Technological University, Singapore, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ian V.","family":"McLoughlin","sequence":"additional","affiliation":[{"name":"University of Science and Technology of China, Heifei, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,2,26]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-2646-6","volume-title":"Elementary functions: algorithms and implementation","author":"Muller J.-M.","year":"1997","unstructured":"J.-M. Muller , Elementary functions: algorithms and implementation . Birkhauser Boston, Inc. , 1997 . J.-M. Muller, Elementary functions: algorithms and implementation. Birkhauser Boston, Inc., 1997."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1975.9794"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1460361.1460365"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(88)90022-6"},{"key":"e_1_3_2_1_5_1","first-page":"301","article-title":"Hardware reciprocation using degree-3 polynomials but only 1 complete multiplication","author":"Tisserand A.","year":"2007","unstructured":"A. Tisserand , \" Hardware reciprocation using degree-3 polynomials but only 1 complete multiplication ,\" in Proceedings of Midwest Symposium on Circuits and Systems , 2007 , pp. 301 -- 304 . A. Tisserand, \"Hardware reciprocation using degree-3 polynomials but only 1 complete multiplication,\" in Proceedings of Midwest Symposium on Circuits and Systems, 2007, pp. 301--304.","journal-title":"Proceedings of Midwest Symposium on Circuits and Systems"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/874057.875197"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.201"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1504\/IJHPSA.2007.013288"},{"key":"e_1_3_2_1_9_1","first-page":"532","volume-title":"Systems and Computers","author":"Brisebarre N.","year":"2004","unstructured":"N. Brisebarre , J. M. Muller , and A. Tisserand , \" Sparse-coefficient polynomial approximations for hardware implementations,\" in Conference Record of Asilomar Conference on Signals , Systems and Computers , 2004 , pp. 532 -- 535 . N. Brisebarre, J. M. Muller, and A. Tisserand, \"Sparse-coefficient polynomial approximations for hardware implementations,\" in Conference Record of Asilomar Conference on Signals, Systems and Computers, 2004, pp. 532--535."},{"key":"e_1_3_2_1_10_1","first-page":"11","article-title":"On determining polynomial evaluation structures for FPGA based custom computing machines","author":"Wojko M.","year":"1999","unstructured":"M. Wojko and H. ElGindy , \" On determining polynomial evaluation structures for FPGA based custom computing machines ,\" in Proceedings of Australasian Computer Architecture Conference , 1999 , pp. 11 -- 22 . M. Wojko and H. ElGindy, \"On determining polynomial evaluation structures for FPGA based custom computing machines,\" in Proceedings of Australasian Computer Architecture Conference, 1999, pp. 11--22.","journal-title":"Proceedings of Australasian Computer Architecture Conference"},{"key":"e_1_3_2_1_11_1","first-page":"21","article-title":"Function evaluation on FPGAs using on-line arithmetic polynomial approximation","author":"Rachid B.","year":"2006","unstructured":"B. Rachid , S. Stephane , and T. Arnaud , \" Function evaluation on FPGAs using on-line arithmetic polynomial approximation ,\" in Proceedings of IEEE North-East Workshop on Circuits and Systems , 2006 , pp. 21 -- 24 . B. Rachid, S. Stephane, and T. Arnaud, \"Function evaluation on FPGAs using on-line arithmetic polynomial approximation,\" in Proceedings of IEEE North-East Workshop on Circuits and Systems, 2006, pp. 21--24.","journal-title":"Proceedings of IEEE North-East Workshop on Circuits and Systems"},{"key":"e_1_3_2_1_12_1","first-page":"1095","volume-title":"Circuits and Systems","author":"Curticpean F.","year":"2002","unstructured":"F. Curticpean and J. Nittylahti , \" Direct digital frequency synthesizers of high spectral purity based on quadratic approximation,\" in Proceedings International Conference on Electronics , Circuits and Systems , 2002 , pp. 1095 -- 1098 . F. Curticpean and J. Nittylahti, \"Direct digital frequency synthesizers of high spectral purity based on quadratic approximation,\" in Proceedings International Conference on Electronics, Circuits and Systems, 2002, pp. 1095--1098."},{"key":"e_1_3_2_1_13_1","first-page":"216","article-title":"Automatic generation of polynomial-based hardware architectures for function evaluation","author":"de Dinechin F.","year":"2010","unstructured":"F. de Dinechin , M. Joldes , and B. Pasca , \" Automatic generation of polynomial-based hardware architectures for function evaluation ,\" in Proceedings of IEEE International Conference on Application-specific Systems Architectures and Processors , 2010 , pp. 216 -- 222 . F. de Dinechin, M. Joldes, and B. Pasca, \"Automatic generation of polynomial-based hardware architectures for function evaluation,\" in Proceedings of IEEE International Conference on Application-specific Systems Architectures and Processors, 2010, pp. 216--222.","journal-title":"Proceedings of IEEE International Conference on Application-specific Systems Architectures and Processors"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2007.50"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2005.34"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.841592"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1070\/RM1966v021n01ABEH004147"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1073\/pnas.58.5.1840"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.62.0239"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223593"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0022-0000(73)80043-1"},{"key":"e_1_3_2_1_22_1","volume-title":"dissertation","author":"Muraoka Y.","year":"1971","unstructured":"Y. Muraoka , \"Parallelism exposure and exploitation in programs,\" Ph. D. dissertation , 1971 . Y. Muraoka, \"Parallelism exposure and exploitation in programs,\" Ph.D. dissertation, 1971."},{"key":"e_1_3_2_1_23_1","volume-title":"Computational and implementation complexity of polynomial evaluation schemes,\" in Proceedings of NORCHIP","author":"Abbas M.","year":"2011","unstructured":"M. Abbas and O. Gustafsson , \" Computational and implementation complexity of polynomial evaluation schemes,\" in Proceedings of NORCHIP , 2011 . M. Abbas and O. Gustafsson, \"Computational and implementation complexity of polynomial evaluation schemes,\" in Proceedings of NORCHIP, 2011."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/SYNASC.2011.17"},{"key":"e_1_3_2_1_25_1","first-page":"151","volume-title":"Dec. 2012","author":"Cheah H. Y.","unstructured":"H. Y. Cheah , S. A. Fahmy , and D. L. Maskell , \" idea: A dsp block based fpga soft processor,\" in Proceedings of the International Conference on Field Programmable Technology (FPT) , Dec. 2012 , pp. 151 -- 158 . H. Y. Cheah, S. A. Fahmy, and D. L. Maskell, \"idea: A dsp block based fpga soft processor,\" in Proceedings of the International Conference on Field Programmable Technology (FPT), Dec. 2012, pp. 151--158."},{"key":"e_1_3_2_1_26_1","volume-title":"Iterative floating point computation using FPGA DSP blocks,\" in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","author":"Brosser F.","year":"2013","unstructured":"F. Brosser , H. Y. Cheah , and S. A. Fahmy , \" Iterative floating point computation using FPGA DSP blocks,\" in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) , 2013 . F. Brosser, H. Y. Cheah, and S. A. Fahmy, \"Iterative floating point computation using FPGA DSP blocks,\" in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2013."},{"key":"e_1_3_2_1_27_1","first-page":"727","volume-title":"Evaluating the efficiency of DSP block synthesis inference from ow graphs,\" in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","author":"Ronak B.","year":"2012","unstructured":"B. Ronak and S. Fahmy , \" Evaluating the efficiency of DSP block synthesis inference from ow graphs,\" in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) , 2012 , pp. 727 -- 730 . B. Ronak and S. Fahmy, \"Evaluating the efficiency of DSP block synthesis inference from ow graphs,\" in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2012, pp. 727--730."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2013.35"},{"key":"e_1_3_2_1_29_1","first-page":"250","volume-title":"Sep. 2009","author":"de Dinechin F.","unstructured":"F. de Dinechin and B. Pasca , \" Large multipliers with fewer DSP blocks,\" in Proceedings of Interenational Conference on Field Programmable Logic and Applications (FPL) , Sep. 2009 , pp. 250 -- 255 . F. de Dinechin and B. Pasca, \"Large multipliers with fewer DSP blocks,\" in Proceedings of Interenational Conference on Field Programmable Logic and Applications (FPL), Sep. 2009, pp. 250--255."},{"key":"e_1_3_2_1_30_1","volume-title":"Gappa. {Online}. Available: http:\/\/gappa.gforge.inria.fr\/","author":"Melquiond G.","year":"2013","unstructured":"G. Melquiond . ( 2013 ) Gappa. {Online}. Available: http:\/\/gappa.gforge.inria.fr\/ . G. Melquiond. (2013) Gappa. {Online}. Available: http:\/\/gappa.gforge.inria.fr\/."},{"key":"e_1_3_2_1_31_1","volume-title":"DC and Switching Characteristics,\" Xilinx Inc","author":"Data Sheet FPGA","year":"2012","unstructured":"Xilinx Inc, \"Virtex-6 FPGA Data Sheet : DC and Switching Characteristics,\" Xilinx Inc , 2012 . Xilinx Inc, \"Virtex-6 FPGA Data Sheet: DC and Switching Characteristics,\" Xilinx Inc, 2012."}],"event":{"name":"FPGA'14: The 2014 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey California USA","acronym":"FPGA'14"},"container-title":["Proceedings of the 2014 ACM\/SIGDA international symposium on Field-programmable gate arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2554688.2554779","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,10]],"date-time":"2023-01-10T07:43:11Z","timestamp":1673336591000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2554688.2554779"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2,26]]},"references-count":31,"alternative-id":["10.1145\/2554688.2554779","10.1145\/2554688"],"URL":"https:\/\/doi.org\/10.1145\/2554688.2554779","relation":{},"subject":[],"published":{"date-parts":[[2014,2,26]]},"assertion":[{"value":"2014-02-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}