{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:47:25Z","timestamp":1759146445413,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,2,26]],"date-time":"2014-02-26T00:00:00Z","timestamp":1393372800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,2,26]]},"DOI":"10.1145\/2554688.2554788","type":"proceedings-article","created":{"date-parts":[[2014,2,18]],"date-time":"2014-02-18T14:10:41Z","timestamp":1392732641000},"page":"11-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Optimizing effective interconnect capacitance for FPGA power reduction"],"prefix":"10.1145","author":[{"given":"Safeen","family":"Huda","sequence":"first","affiliation":[{"name":"University of Toronto, Toronto, ON, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jason","family":"Anderson","sequence":"additional","affiliation":[{"name":"University of Toronto, Toronto, ON, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hirotaka","family":"Tamura","sequence":"additional","affiliation":[{"name":"Fujitsu Laboratories Limited, Kawasaki, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,2,26]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966750"},{"key":"e_1_3_2_1_2_1","first-page":"1","article-title":"High-performance and low-voltage challenges for sub-45nm microprocessor circuits","volume":"2005","author":"Krishnamurthy R.","year":"2005","unstructured":"R. Krishnamurthy , S. Mathew , M. Anders , S. Hsu , H. Kaul , and S. Borkar , \" High-performance and low-voltage challenges for sub-45nm microprocessor circuits ,\" in ASICON 2005 , vol. 1 , 2005 , pp. 283--286. R. Krishnamurthy, S. Mathew, M. Anders, S. Hsu, H. Kaul, and S. Borkar, \"High-performance and low-voltage challenges for sub-45nm microprocessor circuits,\" in ASICON 2005, vol. 1, 2005, pp. 283--286.","journal-title":"ASICON"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.820651"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.856795"},{"key":"e_1_3_2_1_5_1","first-page":"e2011","article-title":"ITRS 2011 Report","author":"ITRS","year":"2011","unstructured":"ITRS , \" ITRS 2011 Report \" {Online}. Available: http:\/\/www.itrs.net\/Links\/ 2011 ITRS\/Hom e2011 .htm ITRS, \"ITRS 2011 Report\" {Online}. Available: http:\/\/www.itrs.net\/Links\/2011ITRS\/Home2011.htm","journal-title":"{Online}. Available: http:\/\/www.itrs.net\/Links\/"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.885731"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950419"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882482"},{"key":"e_1_3_2_1_9_1","unstructured":"Altera personal communication.  Altera personal communication."},{"key":"e_1_3_2_1_10_1","first-page":"373","article-title":"Simultaneous wire sizing and wire spacing in post-layout performance optimization","author":"He J.-A.","year":"1998","unstructured":"J.-A. He and H. Kobayashi , \" Simultaneous wire sizing and wire spacing in post-layout performance optimization ,\" in ASP-DAC , 1998 , pp. 373 -- 378 . J.-A. He and H. Kobayashi, \"Simultaneous wire sizing and wire spacing in post-layout performance optimization,\" in ASP-DAC, 1998, pp. 373--378.","journal-title":"ASP-DAC"},{"key":"e_1_3_2_1_11_1","first-page":"21","article-title":"Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing","author":"Moiseev K.","year":"2006","unstructured":"K. Moiseev , S. Wimer , and A. Kolodny , \" Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing ,\" in IEEE ISCAS , 2006 , pp. 21 -- 24 . K. Moiseev, S. Wimer, and A. Kolodny, \"Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing,\" in IEEE ISCAS, 2006, pp. 21--24.","journal-title":"IEEE ISCAS"},{"key":"e_1_3_2_1_12_1","first-page":"171","article-title":"Circuit design, transistor sizing and wire layout of FPGA interconnect","author":"Betz V.","year":"1999","unstructured":"V. Betz and J. Rose , \" Circuit design, transistor sizing and wire layout of FPGA interconnect ,\" in IEEE CICC , 1999 , pp. 171 -- 174 . V. Betz and J. Rose, \"Circuit design, transistor sizing and wire layout of FPGA interconnect,\" in IEEE CICC, 1999, pp. 171--174.","journal-title":"IEEE"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360292"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145708"},{"key":"e_1_3_2_1_16_1","volume-title":"dissertation","author":"Wilton S. J.","year":"1997","unstructured":"S. J. Wilton , \"Architecture and algorithms for field-programmable gate arrays with embedded memory,\" Ph. D. dissertation , 1997 . S. J. Wilton, \"Architecture and algorithms for field-programmable gate arrays with embedded memory,\" Ph.D. dissertation, 1997."},{"key":"e_1_3_2_1_17_1","first-page":"1","article-title":"Activity estimation for field-programmable gate arrays","author":"Lamoureux J.","year":"2006","unstructured":"J. Lamoureux and S. Wilton , \" Activity estimation for field-programmable gate arrays ,\" in IEEE FPL , 2006 , pp. 1 -- 8 . J. Lamoureux and S. Wilton, \"Activity estimation for field-programmable gate arrays,\" in IEEE FPL, 2006, pp. 1--8.","journal-title":"IEEE FPL"}],"event":{"name":"FPGA'14: The 2014 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey California USA","acronym":"FPGA'14"},"container-title":["Proceedings of the 2014 ACM\/SIGDA international symposium on Field-programmable gate arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2554688.2554788","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2554688.2554788","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:34:20Z","timestamp":1750232060000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2554688.2554788"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2,26]]},"references-count":17,"alternative-id":["10.1145\/2554688.2554788","10.1145\/2554688"],"URL":"https:\/\/doi.org\/10.1145\/2554688.2554788","relation":{},"subject":[],"published":{"date-parts":[[2014,2,26]]},"assertion":[{"value":"2014-02-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}