{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T07:29:41Z","timestamp":1761895781284,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2014,1,22]],"date-time":"2014-01-22T00:00:00Z","timestamp":1390348800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100004963","name":"Seventh Framework Programme","doi-asserted-by":"publisher","award":["318693"],"award-info":[{"award-number":["318693"]}],"id":[{"id":"10.13039\/501100004963","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2014,1,22]]},"DOI":"10.1145\/2555486.2555491","type":"proceedings-article","created":{"date-parts":[[2014,1,14]],"date-time":"2014-01-14T13:40:06Z","timestamp":1389706806000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":44,"title":["System-level power estimation tool for embedded processor based platforms"],"prefix":"10.1145","author":[{"given":"Santhosh Kumar","family":"Rethinagiri","sequence":"first","affiliation":[{"name":"BSC-Microsoft Research Center"}]},{"given":"Oscar","family":"Palomar","sequence":"additional","affiliation":[{"name":"BSC-Microsoft Research Center"}]},{"given":"Rabie","family":"Ben Atitallah","sequence":"additional","affiliation":[{"name":"LAMIH, Universit\u00e9 de Valenciennes"}]},{"given":"Smail","family":"Niar","sequence":"additional","affiliation":[{"name":"LAMIH, Universit\u00e9 de Valenciennes"}]},{"given":"Osman","family":"Unsal","sequence":"additional","affiliation":[{"name":"BSC-Microsoft Research Center"}]},{"given":"Adrian Cristal","family":"Kestelman","sequence":"additional","affiliation":[{"name":"BSC-Microsoft Research Center"}]}],"member":"320","published-online":{"date-parts":[[2014,1,22]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/566726.566736"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2010.5603737"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2007.01.002"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/348019.348081"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICSAMOS.2010.5642102"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReCoSoC.2012.6322869"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224100"},{"key":"e_1_3_2_1_10_1","volume-title":"A power-constrained mpu roadmap for the international technology roadmap for semiconductors (itrs)","author":"Jeong K.","year":"2010","unstructured":"K. Jeong and A. B. Kahng . A power-constrained mpu roadmap for the international technology roadmap for semiconductors (itrs) , 2010 . K. Jeong and A. B. Kahng. A power-constrained mpu roadmap for the international technology roadmap for semiconductors (itrs), 2010."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/968878.968987"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.335013"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-642-11515-8","volume-title":"High Performance Embedded Architectures and Compilers: HiPEAC","author":"Patt Y.","year":"2010","unstructured":"Y. Patt , P. Foglia , E. Duesterwald , P. Faraboschi , and X. Martorell . High Performance Embedded Architectures and Compilers: HiPEAC 2010 , Pisa, Italy . Lecture Notes in Computer Science\/Theoretical Computer Science and General Issues. Springer , 2010. Y. Patt, P. Foglia, E. Duesterwald, P. Faraboschi, and X. Martorell. High Performance Embedded Architectures and Compilers: HiPEAC 2010, Pisa, Italy. Lecture Notes in Computer Science\/Theoretical Computer Science and General Issues. Springer, 2010."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.5555\/580549.835367"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2011.6089692"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/DASIP.2011.6136852"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2206781.2206839"},{"key":"e_1_3_2_1_19_1","volume-title":"Cacti 5.0","author":"Thoziyoor S.","year":"2007","unstructured":"S. Thoziyoor and N. Muralimanohar . Cacti 5.0 , 2007 . S. Thoziyoor and N. Muralimanohar. Cacti 5.0, 2007."},{"key":"e_1_3_2_1_20_1","first-page":"326","volume-title":"Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication, VLSID '96","author":"Tiwari V.","unstructured":"V. Tiwari , S. Malik , A. Wolfe , and M. T.-C. Lee . Instruction level power analysis and optimization of software . In Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication, VLSID '96 , pages 326 --, Washington, DC, USA, 1996. IEEE Computer Society. V. Tiwari, S. Malik, A. Wolfe, and M. T.-C. Lee. Instruction level power analysis and optimization of software. In Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication, VLSID '96, pages 326--, Washington, DC, USA, 1996. IEEE Computer Society."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370865"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339659"}],"event":{"name":"RAPIDO '14: Rapid Simulation and Performance Evaluation: Methods and Tools","sponsor":["HiPEAC HiPEAC Network of Excellence"],"location":"Vienna Austria","acronym":"RAPIDO '14"},"container-title":["Proceedings of the 6th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2555486.2555491","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2555486.2555491","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:35:05Z","timestamp":1750232105000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2555486.2555491"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,1,22]]},"references-count":21,"alternative-id":["10.1145\/2555486.2555491","10.1145\/2555486"],"URL":"https:\/\/doi.org\/10.1145\/2555486.2555491","relation":{},"subject":[],"published":{"date-parts":[[2014,1,22]]},"assertion":[{"value":"2014-01-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}