{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,15]],"date-time":"2026-10-15T16:31:00Z","timestamp":1792081860871,"version":"4.4.0"},"reference-count":120,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2014,3,10]],"date-time":"2014-03-10T00:00:00Z","timestamp":1394409600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100004963","name":"Seventh Framework Programme","doi-asserted-by":"publisher","award":["IST-214373"],"award-info":[{"award-number":["IST-214373"]}],"id":[{"id":"10.13039\/501100004963","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2014,12,5]]},"abstract":"<jats:p>\n            A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed\n            <jats:italic>a priori<\/jats:italic>\n            . Perhaps paradoxically, this problem has become more difficult by the introduction of performance-enhancing architectural elements, such as caches, pipelines, and multithreading, which introduce a large degree of uncertainty and make guarantees harder to provide. The intention of this article is to summarize the current state of the art in research concerning how to build predictable yet performant systems. We suggest precise definitions for the concept of \u201cpredictability\u201d, and present predictability concerns at different abstraction levels in embedded system design. First, we consider timing predictability of processor instruction sets. Thereafter, we consider how programming languages can be equipped with predictable timing semantics, covering both a language-based approach using the synchronous programming paradigm, as well as an environment that provides timing semantics for a mainstream programming language (in this case C). We present techniques for achieving timing predictability on multicores. Finally, we discuss how to handle predictability at the level of networked embedded systems where randomly occurring errors must be considered.\n          <\/jats:p>","DOI":"10.1145\/2560033","type":"journal-article","created":{"date-parts":[[2014,3,18]],"date-time":"2014-03-18T12:09:07Z","timestamp":1395144547000},"page":"1-37","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":90,"title":["Building timing predictable embedded systems"],"prefix":"10.1145","volume":"13","author":[{"given":"Philip","family":"Axer","sequence":"first","affiliation":[{"name":"TU Braunschweig"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rolf","family":"Ernst","sequence":"additional","affiliation":[{"name":"TU Braunschweig"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Heiko","family":"Falk","sequence":"additional","affiliation":[{"name":"Ulm University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alain","family":"Girault","sequence":"additional","affiliation":[{"name":"INRIA and University of Grenoble"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Daniel","family":"Grund","sequence":"additional","affiliation":[{"name":"Saarland University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nan","family":"Guan","sequence":"additional","affiliation":[{"name":"Uppsala University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bengt","family":"Jonsson","sequence":"additional","affiliation":[{"name":"Uppsala University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Peter","family":"Marwedel","sequence":"additional","affiliation":[{"name":"TU Dortmund"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jan","family":"Reineke","sequence":"additional","affiliation":[{"name":"Saarland University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Christine","family":"Rochange","sequence":"additional","affiliation":[{"name":"University of Toulouse"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Maurice","family":"Sebastian","sequence":"additional","affiliation":[{"name":"TU Braunschweig"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Reinhard Von","family":"Hanxleden","sequence":"additional","affiliation":[{"name":"CAU Kiel"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Reinhard","family":"Wilhelm","sequence":"additional","affiliation":[{"name":"Saarland University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wang","family":"Yi","sequence":"additional","affiliation":[{"name":"Uppsala University"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2014,3,10]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289877"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the International Conference on Parallel Architectures and Compilation Techniques. 25--34","author":"Albonesi D. H.","unstructured":"D. H. Albonesi and I. Koren . 1994. Tradeoffs in the design of single chip multiprocessors . In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques. 25--34 . D. H. Albonesi and I. Koren. 1994. Tradeoffs in the design of single chip multiprocessors. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques. 25--34."},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the International Conference on Formal Methods and Models for Codesign.159--168","author":"Andalam S.","unstructured":"S. Andalam , P. Roop , and A. Girault . 2010. Predictable multithreading of embedded applications using PRET-C . In Proceedings of the International Conference on Formal Methods and Models for Codesign.159--168 . S. Andalam, P. Roop, and A. Girault. 2010. Predictable multithreading of embedded applications using PRET-C. In Proceedings of the International Conference on Formal Methods and Models for Codesign.159--168."},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the Conference on Design Automation and Test in Europe. 204--209","author":"Andalam S.","unstructured":"S. Andalam , P. Roop , and A. Girault . 2011. Pruning infeasible paths for tight WCRT analysis of synchronous programs . In Proceedings of the Conference on Design Automation and Test in Europe. 204--209 . S. Andalam, P. Roop, and A. Girault. 2011. Pruning infeasible paths for tight WCRT analysis of synchronous programs. In Proceedings of the Conference on Design Automation and Test in Europe. 204--209."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1851166.1851172"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.2008.33"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.1985.231893"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039396"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/956418.956614"},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of the International Conference on Architecture of Computing Systems. 161--172","author":"Barre J.","unstructured":"J. Barre , C. Rochange , and P. Sainrat . 2008. A predictable simultaneous multithreading scheme for hard real-time . In Proceedings of the International Conference on Architecture of Computing Systems. 161--172 . J. Barre, C. Rochange, and P. Sainrat. 2008. A predictable simultaneous multithreading scheme for hard real-time. In Proceedings of the International Conference on Architecture of Computing Systems. 161--172."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2007.48"},{"key":"e_1_2_1_12_1","volume-title":"Proceedings of the International Workshop on Operating Systems Platforms for Embedded Real-Time Applications. 33--44","author":"Bastoni A.","unstructured":"A. Bastoni , B. B. Brandenburg , and J. H. Anderson . 2010a. Cache-related preemption and migration delays: Empirical approximation and impact on schedulability . In Proceedings of the International Workshop on Operating Systems Platforms for Embedded Real-Time Applications. 33--44 . A. Bastoni, B. B. Brandenburg, and J. H. Anderson. 2010a. Cache-related preemption and migration delays: Empirical approximation and impact on schedulability. In Proceedings of the International Workshop on Operating Systems Platforms for Embedded Real-Time Applications. 33--44."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2010.23"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2011.20"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.805826"},{"key":"e_1_2_1_16_1","volume-title":"Proceedings of the International Workshop on Worst-Case Execution Time Analysis.","author":"Berg C.","year":"2006","unstructured":"C. Berg . 2006 . PLRU cache domino effects . In Proceedings of the International Workshop on Worst-Case Execution Time Analysis. C. Berg. 2006. PLRU cache domino effects. In Proceedings of the International Workshop on Worst-Case Execution Time Analysis."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1090\/S0002-9939-01-06247-5"},{"key":"e_1_2_1_18_1","volume-title":"Proof, Language, and Interaction: Essays in Honour of Robin Milner","author":"Berry G.","unstructured":"G. Berry . 2000. The foundations of Esterel . In Proof, Language, and Interaction: Essays in Honour of Robin Milner , G. Plotkin, C. P. Stirling, and M. Tofte, Eds., MIT Press , Cambridge, MA , 425--454. G. Berry. 2000. The foundations of Esterel. In Proof, Language, and Interaction: Essays in Honour of Robin Milner, G. Plotkin, C. P. Stirling, and M. Tofte, Eds., MIT Press, Cambridge, MA, 425--454."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1155\/2008\/594129"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1016\/0141-9331(96)89278-7"},{"key":"e_1_2_1_23_1","volume-title":"Proceedings of the Euromicro Conference on Real-Time Systems. 134--141","author":"Broster I.","unstructured":"I. Broster , G. Bernat , and A. Burns . 2002a. Weakly hard real-time constraints on controller area network . In Proceedings of the Euromicro Conference on Real-Time Systems. 134--141 . I. Broster, G. Bernat, and A. Burns. 2002a. Weakly hard real-time constraints on controller area network. In Proceedings of the Euromicro Conference on Real-Time Systems. 134--141."},{"key":"e_1_2_1_24_1","volume-title":"Proceedings of the International Real-Time Systems Symposium. 269--278","author":"Broster I.","unstructured":"I. Broster , A. Burns , and G. Rodr\u00edguez-Navas . 2002b. Probabilistic analysis of CAN with faults . In Proceedings of the International Real-Time Systems Symposium. 269--278 . I. Broster, A. Burns, and G. Rodr\u00edguez-Navas. 2002b. Probabilistic analysis of CAN with faults. In Proceedings of the International Real-Time Systems Symposium. 269--278."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024787"},{"key":"e_1_2_1_26_1","volume-title":"Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications","author":"Buttazzo G.","unstructured":"G. Buttazzo . 2011. Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications 3 rd Ed. Springer . G. Buttazzo. 2011. Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications 3rd Ed. Springer.","edition":"3"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2006.27"},{"key":"e_1_2_1_28_1","unstructured":"CAN. 1991. CAN specification 2.0. Robert Bosch GmbH.  CAN. 1991. CAN specification 2.0. Robert Bosch GmbH."},{"key":"e_1_2_1_29_1","unstructured":"J. Carpenter S. Funk P. Holman A. Srinivasan J. Anderson and S. Baruah. 2004. A categorization of real-time multiprocessor scheduling problems and algorithms. In Handbook on Scheduling Algorithms Methods and Models Chapman Hall\/CRC Boca Raton FL.  J. Carpenter S. Funk P. Holman A. Srinivasan J. Anderson and S. Baruah. 2004. A categorization of real-time multiprocessor scheduling problems and algorithms. In Handbook on Scheduling Algorithms Methods and Models Chapman Hall\/CRC Boca Raton FL."},{"key":"e_1_2_1_30_1","volume-title":"Proceedings of the International CAN Conference. 1--20","author":"Charzinski J.","year":"1994","unstructured":"J. Charzinski . 1994 . Performance of the error detection mechanisms in CAN . In Proceedings of the International CAN Conference. 1--20 . J. Charzinski. 1994. Performance of the error detection mechanisms in CAN. In Proceedings of the International CAN Conference. 1--20."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1811212.1811220"},{"key":"e_1_2_1_32_1","volume-title":"Tech. Rep. 430","author":"Chiou D.","year":"1999","unstructured":"D. Chiou , L. Rudolph , S. Devadas , L. Randolph , and B. S. Ang . 1999 . Dynamic cache partitioning via columnization. Tech. Rep. 430 , Massachusetts Institute of Technology . D. Chiou, L. Rudolph, S. Devadas, L. Randolph, and B. S. Ang. 1999. Dynamic cache partitioning via columnization. Tech. Rep. 430, Massachusetts Institute of Technology."},{"key":"e_1_2_1_33_1","volume-title":"Proceedings of Embedded Real Time Software and Systems. 36--42","author":"Cullmann C.","unstructured":"C. Cullmann , C. Ferdinand , G. Gebhard , D. Grund , C. Maiza , J. Reineke , B. Triquet , and R. Wilhelm . 2010. Predictability considerations in the design of multi-core embedded systems . In Proceedings of Embedded Real Time Software and Systems. 36--42 . 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Syst. 2007.","DOI":"10.1186\/1687-3963-2007-052651"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1086297.1086326"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630101"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/2038698.2038722"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-010-9101-x"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/2380356.2380389"},{"key":"e_1_2_1_43_1","volume-title":"Proceedings of the International Workshop of Real-Time Networks. 15--18","author":"Ferreira J.","unstructured":"J. Ferreira , A. Oliveira , P. Fonseca , and J. Fonseca . 2004. An experiment to assess bit error rate in CAN . In Proceedings of the International Workshop of Real-Time Networks. 15--18 . J. Ferreira, A. Oliveira, P. Fonseca, and J. Fonseca. 2004. An experiment to assess bit error rate in CAN. In Proceedings of the International Workshop of Real-Time Networks. 15--18."},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/1289927.1289968"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2012.11"},{"key":"e_1_2_1_46_1","volume-title":"Proceedings of the Workshop on Predictability and Performance in Embedded Systems. 22--31","author":"Grund D.","unstructured":"D. Grund , J. Reineke , and R. Wilhelm . 2011. A template for predictability definitions with supporting evidence . In Proceedings of the Workshop on Predictability and Performance in Embedded Systems. 22--31 . D. Grund, J. Reineke, and R. Wilhelm. 2011. A template for predictability definitions with supporting evidence. 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IEC 61508 Edition 2.0: Functional safety of electrical\/electronic\/programmable electronic safety-related systems. http:\/\/www.iec.ch\/functionalsafety\/standards\/page2.htm."},{"key":"e_1_2_1_55_1","volume-title":"ISO 26262: Road vehicles -- functional safety","author":"ISO","unstructured":"ISO 26262. 2011. ISO 26262: Road vehicles -- functional safety . International Organization for Standardization . ISO 26262. 2011. ISO 26262: Road vehicles -- functional safety. International Organization for Standardization."},{"key":"e_1_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/DELTA.2006.83"},{"key":"e_1_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/1450135.1450175"},{"key":"e_1_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/1450058.1450078"},{"key":"e_1_2_1_59_1","volume-title":"Proceedings of the Euromicro Conference on Real-Time Systems. 29--36","author":"Kirner R.","unstructured":"R. Kirner and P. Puschner . 2001. Transformation of path information for WCET analysis during compilation . In Proceedings of the Euromicro Conference on Real-Time Systems. 29--36 . R. Kirner and P. Puschner. 2001. Transformation of path information for WCET analysis during compilation. In Proceedings of the Euromicro Conference on Real-Time Systems. 29--36."},{"key":"e_1_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1109\/TR.1969.5216961"},{"key":"e_1_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2009.33"},{"key":"e_1_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.259424"},{"key":"e_1_2_1_63_1","volume-title":"Proceedings of the Euromicro Conference on Real-Time Systems. 188--195","author":"Lauzac S.","unstructured":"S. Lauzac , R. G. Melhem , and D. Moss\u00e9 . 1998. Comparison of global and partitioning schemes for scheduling rate monotonic tasks on a multiprocessor . In Proceedings of the Euromicro Conference on Real-Time Systems. 188--195 . S. Lauzac, R. G. Melhem, and D. Moss\u00e9. 1998. Comparison of global and partitioning schemes for scheduling rate monotonic tasks on a multiprocessor. In Proceedings of the Euromicro Conference on Real-Time Systems. 188--195."},{"key":"e_1_2_1_64_1","volume-title":"Proceedings of the International Conference on Computer Application in Transportation Systems.","author":"Legoff G.","year":"1996","unstructured":"G. Legoff . 1996 . Using synchronous languages for interlocking . In Proceedings of the International Conference on Computer Application in Transportation Systems. G. Legoff. 1996. Using synchronous languages for interlocking. In Proceedings of the International Conference on Computer Application in Transportation Systems."},{"key":"e_1_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.246"},{"key":"e_1_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2009.32"},{"key":"e_1_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1145\/1450095.1450117"},{"key":"e_1_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/321738.321743"},{"key":"e_1_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378622"},{"key":"e_1_2_1_70_1","volume-title":"Real-Time Systems","author":"Liu J. W. S.","unstructured":"J. W. S. Liu . 2000. Real-Time Systems . Prentice Hall , Upper Saddle River, NJ. J. W. S. Liu. 2000. Real-Time Systems. Prentice Hall, Upper Saddle River, NJ."},{"key":"e_1_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2009.11"},{"key":"e_1_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2011.05.006"},{"key":"e_1_2_1_73_1","volume-title":"Proceedings of the International Real-Time Systems Symposium. 12--21","author":"Lundqvist T.","unstructured":"T. Lundqvist and P. Stenstr\u00f6m . 1999. Timing anomalies in dynamically scheduled microprocessors . In Proceedings of the International Real-Time Systems Symposium. 12--21 . T. Lundqvist and P. Stenstr\u00f6m. 1999. Timing anomalies in dynamically scheduled microprocessors. In Proceedings of the International Real-Time Systems Symposium. 12--21."},{"key":"e_1_2_1_74_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2010.30"},{"key":"e_1_2_1_75_1","volume-title":"Proceedings of the International Workshop on Worst-Case Execution Time Analysis. 13--24","author":"Maksoud M. A.","unstructured":"M. A. Maksoud and J. Reineke . 2012. An empirical evaluation of the influence of the load-store unit on WCET analysis . In Proceedings of the International Workshop on Worst-Case Execution Time Analysis. 13--24 . M. A. Maksoud and J. Reineke. 2012. An empirical evaluation of the influence of the load-store unit on WCET analysis. In Proceedings of the International Workshop on Worst-Case Execution Time Analysis. 13--24."},{"key":"e_1_2_1_76_1","volume-title":"Proceedings of the International Conference on Computer Design. 371--376","author":"Mische J.","unstructured":"J. Mische , S. Uhrig , F. Kluge , and T. Ungerer . 2008. Exploiting spare resources of in-order SMT processors executing hard real-time threads . In Proceedings of the International Conference on Computer Design. 371--376 . J. Mische, S. Uhrig, F. Kluge, and T. Ungerer. 2008. Exploiting spare resources of in-order SMT processors executing hard real-time threads. In Proceedings of the International Conference on Computer Design. 371--376."},{"key":"e_1_2_1_77_1","volume-title":"Proceedings of the Annual Workshop on Circuits, Systems and Signal Processing. 86--90","author":"Molnos A. M.","year":"2004","unstructured":"A. M. Molnos , M. J. M. Heijligers , S. D. Cotofana , and J. T. J. van Eijndhoven . 2004 . Cache partitioning options for compositional multimedia applications . In Proceedings of the Annual Workshop on Circuits, Systems and Signal Processing. 86--90 . A. M. Molnos, M. J. M. Heijligers, S. D. Cotofana, and J. T. J. van Eijndhoven. 2004. Cache partitioning options for compositional multimedia applications. In Proceedings of the Annual Workshop on Circuits, Systems and Signal Processing. 86--90."},{"key":"e_1_2_1_78_1","doi-asserted-by":"publisher","DOI":"10.1145\/216636.216677"},{"key":"e_1_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.1016\/S1383-7621(99)00016-8"},{"key":"e_1_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1109\/EDCC.2012.27"},{"key":"e_1_2_1_81_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555764"},{"key":"e_1_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2010.2041634"},{"key":"e_1_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2011.34"},{"key":"e_1_2_1_84_1","doi-asserted-by":"crossref","unstructured":"D. Paret and R. Riesco. 2007. Multiplexed Networks for Embedded Systems: CAN LIN Flexray Safe-by- Wire. &mldr; John Wiley & Sons Hoboken NJ.  D. Paret and R. Riesco. 2007. Multiplexed Networks for Embedded Systems: CAN LIN Flexray Safe-by- Wire. &mldr; John Wiley & Sons Hoboken NJ.","DOI":"10.1002\/9780470511770"},{"key":"e_1_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.1109\/24.370218"},{"key":"e_1_2_1_86_1","volume-title":"Proceedings of the Conference on Design Automation and Test in Europe. 741--746","author":"Pellizzoni R.","unstructured":"R. Pellizzoni , A. Schranzhofer , J.-J. Chen , M. Caccamo , and L. Thiele . 2010. Worst case delay analysis for memory interference in multicore systems . In Proceedings of the Conference on Design Automation and Test in Europe. 741--746 . R. Pellizzoni, A. Schranzhofer, J.-J. Chen, M. Caccamo, and L. Thiele. 2010. Worst case delay analysis for memory interference in multicore systems. In Proceedings of the Conference on Design Automation and Test in Europe. 741--746."},{"key":"e_1_2_1_87_1","volume-title":"Proceedings of the International Workshop on Worst-Case Execution Time Analysis. 78--88","author":"Plazar S.","unstructured":"S. Plazar , P. Lokuciejewski , and P. Marwedel . 2009. WCET-aware software based cache partitioning for multi-task real-time systems . In Proceedings of the International Workshop on Worst-Case Execution Time Analysis. 78--88 . S. Plazar, P. Lokuciejewski, and P. Marwedel. 2009. WCET-aware software based cache partitioning for multi-task real-time systems. In Proceedings of the International Workshop on Worst-Case Execution Time Analysis. 78--88."},{"key":"e_1_2_1_88_1","unstructured":"D. Potop-Butucaru S. A. Edwards and G. Berry. 2007. Compiling Esterel. Springer.   D. Potop-Butucaru S. A. Edwards and G. Berry. 2007. Compiling Esterel. Springer."},{"key":"e_1_2_1_89_1","volume-title":"Software Fault Tolerance\u2014Techniques and Implementation","author":"Pullum L.","unstructured":"L. Pullum . 2001. Software Fault Tolerance\u2014Techniques and Implementation . Artech House . L. Pullum. 2001. Software Fault Tolerance\u2014Techniques and Implementation. Artech House."},{"key":"e_1_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086713"},{"key":"e_1_2_1_91_1","doi-asserted-by":"publisher","DOI":"10.1145\/2435227.2435238"},{"key":"e_1_2_1_92_1","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039388"},{"key":"e_1_2_1_93_1","volume-title":"Proceedings of the International Workshop on Worst-Case Execution Time Analysis.","author":"Reineke J.","unstructured":"J. Reineke , B. Wachter , S. Thesing , R. Wilhelm , I. Polian , J. Eisinger , and B. Becker . 2006. A definition and classification of timing anomalies . In Proceedings of the International Workshop on Worst-Case Execution Time Analysis. J. Reineke, B. Wachter, S. Thesing, R. Wilhelm, I. Polian, J. Eisinger, and B. Becker. 2006. A definition and classification of timing anomalies. In Proceedings of the International Workshop on Worst-Case Execution Time Analysis."},{"key":"e_1_2_1_94_1","doi-asserted-by":"publisher","DOI":"10.1145\/1062261.1062312"},{"key":"e_1_2_1_95_1","volume-title":"Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems. 344--351","author":"Rokas K.","unstructured":"K. Rokas , Y. Makris , and D. Gizopoulos . 2003. Low cost convolutional code based concurrent error detection in FSMs . In Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems. 344--351 . K. Rokas, Y. Makris, and D. Gizopoulos. 2003. Low cost convolutional code based concurrent error detection in FSMs. In Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems. 344--351."},{"key":"e_1_2_1_96_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2007.13"},{"key":"e_1_2_1_97_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Application. 945--954","author":"Salcic Z. A.","unstructured":"Z. A. Salcic , P. S. Roop , M. Biglari-Abhari , and A. Bigdeli . 2002. REFLIX: A processor core for reactive embedded applications . In Proceedings of the International Conference on Field Programmable Logic and Application. 945--954 . Z. A. Salcic, P. S. Roop, M. Biglari-Abhari, and A. Bigdeli. 2002. REFLIX: A processor core for reactive embedded applications. In Proceedings of the International Conference on Field Programmable Logic and Application. 945--954."},{"key":"e_1_2_1_98_1","doi-asserted-by":"publisher","DOI":"10.1109\/24.52622"},{"key":"e_1_2_1_99_1","volume-title":"Proceedings of the Conference on Design Automation and Test in Europe. 759--764","author":"Schliecker S.","unstructured":"S. Schliecker , M. Negrean , and R. Ernst . 2010. Bounding the shared resource load for the performance analysis of multiprocessor systems . In Proceedings of the Conference on Design Automation and Test in Europe. 759--764 . S. Schliecker, M. Negrean, and R. Ernst. 2010. Bounding the shared resource load for the performance analysis of multiprocessor systems. In Proceedings of the Conference on Design Automation and Test in Europe. 759--764."},{"key":"e_1_2_1_101_1","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2011.19"},{"key":"e_1_2_1_102_1","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2009.10"},{"key":"e_1_2_1_103_1","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024420"},{"key":"e_1_2_1_104_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01995673"},{"key":"e_1_2_1_105_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2005.45"},{"key":"e_1_2_1_106_1","doi-asserted-by":"publisher","DOI":"10.1023\/B:TIME.0000045316.66276.6e"},{"key":"e_1_2_1_107_1","volume-title":"Tech. Rep. YCS229, Department of Computer Science","author":"Tindell K.","year":"1994","unstructured":"K. Tindell and A. Burns . 1994 . Guaranteed message latencies for distributed safety-critical hard real-time control networks. Tech. Rep. YCS229, Department of Computer Science , University of York. K. Tindell and A. Burns. 1994. Guaranteed message latencies for distributed safety-critical hard real-time control networks. Tech. Rep. YCS229, Department of Computer Science, University of York."},{"key":"e_1_2_1_108_1","doi-asserted-by":"publisher","DOI":"10.1016\/0967-0661(95)00112-8"},{"key":"e_1_2_1_109_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.78"},{"key":"e_1_2_1_110_1","volume-title":"Introduction to Coding Theory","author":"Van Lint J.","unstructured":"J. Van Lint . 1999. Introduction to Coding Theory 3 rd Ed. Springer . J. Van Lint. 1999. Introduction to Coding Theory 3rd Ed. Springer.","edition":"3"},{"key":"e_1_2_1_111_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629335.1629366"},{"key":"e_1_2_1_112_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1976.10239"},{"key":"e_1_2_1_113_1","doi-asserted-by":"publisher","DOI":"10.1145\/2248418.2248425"},{"key":"e_1_2_1_114_1","unstructured":"WCC. 2014. WCET-aware Compilation. http:\/\/ls12-www.cs.tu-dortmund.de\/research\/activities\/wcc.  WCC. 2014. WCET-aware Compilation. http:\/\/ls12-www.cs.tu-dortmund.de\/research\/activities\/wcc."},{"key":"e_1_2_1_115_1","doi-asserted-by":"crossref","unstructured":"S. Wicker and V. Bhargava. 1999. Reed-Solomon Codes and Their Applications. IEEE.   S. Wicker and V. Bhargava. 1999. Reed-Solomon Codes and Their Applications. IEEE.","DOI":"10.1109\/9780470546345"},{"key":"e_1_2_1_116_1","doi-asserted-by":"publisher","DOI":"10.1145\/1347375.1347389"},{"key":"e_1_2_1_117_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2013287"},{"key":"e_1_2_1_118_1","volume-title":"Proceedings of the Military Communications Conference. 287--292","author":"Wolf J.","unstructured":"J. Wolf and R. Blakeney . 1988. An exact evaluation of the probability of undetected error for certain shortened binary CRC codes . In Proceedings of the Military Communications Conference. 287--292 . J. Wolf and R. Blakeney. 1988. An exact evaluation of the probability of undetected error for certain shortened binary CRC codes. In Proceedings of the Military Communications Conference. 287--292."},{"key":"e_1_2_1_119_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1982.1095473"},{"key":"e_1_2_1_120_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.entcs.2008.01.005"},{"key":"e_1_2_1_121_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2005.29"},{"key":"e_1_2_1_122_1","doi-asserted-by":"publisher","DOI":"10.1145\/1113841.1113842"},{"key":"e_1_2_1_123_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2009.39"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2560033","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2560033","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:10:21Z","timestamp":1750234221000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2560033"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3,10]]},"references-count":120,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2014,12,5]]}},"alternative-id":["10.1145\/2560033"],"URL":"https:\/\/doi.org\/10.1145\/2560033","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,3,10]]},"assertion":[{"value":"2012-06-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-11-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-03-10","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}