{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:20:51Z","timestamp":1750306851970,"version":"3.41.0"},"reference-count":27,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2014,3,10]],"date-time":"2014-03-10T00:00:00Z","timestamp":1394409600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council Taiwan","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2014,12,5]]},"abstract":"<jats:p>In order to satisfy the growing demand for high-performance computing in modern embedded devices, several architectural and microarchitectural enhancements have been implemented in processor architectures. Extended instruction (EI) is often used for architectural enhancement, while issuing multiple instructions is a common approach for microarchitectural enhancement. The impact of combining both of these approaches in the same design is not well understood. While previous studies have shown that EI can potentially improve performance in some applications on certain multiple-issue architectures, the algorithms used to identify EI for multiple-issue architectures yield only limited performance improvement. This is because not all arithmetic operations are suited for EI for multiple-issue architectures. To explore the full potential of EI for multiple-issue architectures, two important factors need to be considered: (1) the execution performance of an application is dominated by critical (located on the critical path) and highly resource-contentious (i.e., having a high probability of being delayed during execution due to hardware resource limitations) operations, and (2) an operation may become critical and\/or highly resource contentious after some operations are added to the EI. This article presents an EI exploration algorithm for multiple-issue architectures that focuses on these two factors. Simulation results show that the proposed algorithm outperforms previously published algorithms.<\/jats:p>","DOI":"10.1145\/2560039","type":"journal-article","created":{"date-parts":[[2014,3,18]],"date-time":"2014-03-18T12:09:07Z","timestamp":1395144547000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Extended Instruction Exploration for Multiple-Issue Architectures"],"prefix":"10.1145","volume":"13","author":[{"given":"I-Wei","family":"Wu","sequence":"first","affiliation":[{"name":"National Chiao Tung University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean Jyh-Jiun","family":"Shann","sequence":"additional","affiliation":[{"name":"National Chiao Tung University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei-Chung","family":"Hsu","sequence":"additional","affiliation":[{"name":"National Taiwan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chung-Ping","family":"Chung","sequence":"additional","affiliation":[{"name":"National Chiao Tung University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2014,3,10]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"ALTERA CORP. 2004. Nios II Processor Reference Handbook. http:\/\/www.altera.com\/literature\/lit-nio2.jsp.  ALTERA CORP. 2004. Nios II Processor Reference Handbook. http:\/\/www.altera.com\/literature\/lit-nio2.jsp."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775897"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878345"},{"volume-title":"Proceedings of the Symposium on High Performance Chips (HotChips).","author":"Clark N. T.","key":"e_1_2_1_4_1","unstructured":"N. T. Clark , H. Zhong , K. Fan , S. Mahlke , K. Flautner , and V. Nieuwenhove . 2004. OptimoDE: Programmable accelerator engines through retargetable customization . In Proceedings of the Symposium on High Performance Chips (HotChips). N. T. Clark, H. Zhong, K. Fan, S. Mahlke, K. Flautner, and V. Nieuwenhove. 2004. OptimoDE: Programmable accelerator engines through retargetable customization. In Proceedings of the Symposium on High Performance Chips (HotChips)."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.156"},{"volume-title":"Proceedings of the Java Optimization Strategies for Embedded Systems Workshop (JOSES).","author":"David G.","key":"e_1_2_1_6_1","unstructured":"G. David , M. A. Ertl , and A. Krall . 2001. A fast Java interpreter . In Proceedings of the Java Optimization Strategies for Embedded Systems Workshop (JOSES). G. David, M. A. Ertl, and A. Krall. 2001. A fast Java interpreter. In Proceedings of the Java Optimization Strategies for Embedded Systems Workshop (JOSES)."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339682"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1968502.1968509"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/951710.951730"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/1128020.1128563"},{"key":"e_1_2_1_11_1","first-page":"42","article-title":"ARC cores encourages plug-ins","volume":"14","author":"Halfhill T. R.","year":"2000","unstructured":"T. R. Halfhill . 2000 . ARC cores encourages plug-ins . Microprocess. Rep. 14 , 4, 42 -- 44 . T. R. Halfhill. 2000. ARC cores encourages plug-ins. Microprocess. Rep. 14, 4, 42--44.","journal-title":"Microprocess. Rep."},{"key":"e_1_2_1_12_1","unstructured":"T. R. Halfhill. 2003a. MIPS embraces configurable technology. Microprocess. Rep.  T. R. Halfhill. 2003a. MIPS embraces configurable technology. Microprocess. Rep."},{"key":"e_1_2_1_13_1","unstructured":"T. R. Halfhill. 2003b. Tensilica's software makes hardware. Microprocess. Rep.  T. R. Halfhill. 2003b. Tensilica's software makes hardware. Microprocess. Rep."},{"volume-title":"Proceedings of the 8th International Workshop on Software and Compilers for Embedded Systems (SCOPES). 17--32","author":"Jain D.","key":"e_1_2_1_14_1","unstructured":"D. Jain , A. Kumar , L. Pozzi , and P. Ienne . 2004. Automatically customising VLIW architectures with coarse grained application-specific functional units . In Proceedings of the 8th International Workshop on Software and Compilers for Embedded Systems (SCOPES). 17--32 . D. Jain, A. Kumar, L. Pozzi, and P. Ienne. 2004. Automatically customising VLIW architectures with coarse grained application-specific functional units. In Proceedings of the 8th International Workshop on Software and Compilers for Embedded Systems (SCOPES). 17--32."},{"key":"e_1_2_1_15_1","volume-title":"LLVM: An infrastructure for multi-stage optimization. Master's thesis. Computer Science Dept.","author":"Lattner C.","year":"2002","unstructured":"C. Lattner . 2002 . LLVM: An infrastructure for multi-stage optimization. Master's thesis. Computer Science Dept. , University of Illinois at Urbana-Champaign , IL. C. Lattner. 2002. LLVM: An infrastructure for multi-stage optimization. Master's thesis. Computer Science Dept., University of Illinois at Urbana-Champaign, IL."},{"volume-title":"Proceedings of the European Design and Test Conference (ED&TC). 31--37","author":"Liem C.","key":"e_1_2_1_16_1","unstructured":"C. Liem , T. May , and P. Paulin . 1994. Instruction-set matching and selection for DSP and ASIP code generation . In Proceedings of the European Design and Test Conference (ED&TC). 31--37 . C. Liem, T. May, and P. Paulin. 1994. Instruction-set matching and selection for DSP and ASIP code generation. In Proceedings of the European Design and Test Conference (ED&TC). 31--37."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818292"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391519"},{"key":"e_1_2_1_19_1","doi-asserted-by":"crossref","unstructured":"L. Pozzi and P. Ienne. 2006. Automatic instruction set extension. In Customizable Embedded Processors Morgan Kaufmann San Mateo CA.  L. Pozzi and P. Ienne. 2006. Automatic instruction set extension. In Customizable Embedded Processors Morgan Kaufmann San Mateo CA.","DOI":"10.1016\/B978-012369526-0\/50008-5"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855950"},{"volume-title":"Proceedings of the 29th Design Automation Conference (DAC). 235--238","author":"Rao D. S.","key":"e_1_2_1_21_1","unstructured":"D. S. Rao and F. J. Kurdahi . 1992. Partitioning by regularity extraction . In Proceedings of the 29th Design Automation Conference (DAC). 235--238 . D. S. Rao and F. J. Kurdahi. 1992. Partitioning by regularity extraction. In Proceedings of the 29th Design Automation Conference (DAC). 235--238."},{"volume-title":"Exploring VLIW ASIP design space using trimaran based framework. Master's thesis. Department of Computer Science and Engineering","author":"Reddy V. S.","key":"e_1_2_1_22_1","unstructured":"V. S. Reddy . 2006. Exploring VLIW ASIP design space using trimaran based framework. Master's thesis. Department of Computer Science and Engineering , Indian Institute of Technology Delhi . V. S. Reddy. 2006. Exploring VLIW ASIP design space using trimaran based framework. Master's thesis. Department of Computer Science and Engineering, Indian Institute of Technology Delhi."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.5555\/1762146.1762172"},{"volume-title":"Proceedings of the IEEE International Conference on Field-Programmable Technologies (ICFPT). 369--372","author":"Stephan W.","key":"e_1_2_1_24_1","unstructured":"W. Stephan , T. V. As , and G. Brown . 2008. &rho;-VEX: A reconfigurable and extensible softcore VLIW processor . In Proceedings of the IEEE International Conference on Field-Programmable Technologies (ICFPT). 369--372 . W. Stephan, T. V. As, and G. Brown. 2008. &rho;-VEX: A reconfigurable and extensible softcore VLIW processor. In Proceedings of the IEEE International Conference on Field-Programmable Technologies (ICFPT). 369--372."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774667"},{"key":"e_1_2_1_26_1","series-title":"Lecture Notes in Computer Science","volume-title":"Proceedings of the 2nd International Conference on High Performance Embedded Architecture and Compilers","author":"Wu I. W.","unstructured":"I. W. Wu , S.-C. Huang , C.-P. Chung , and J.-J. Shann . 2007. Instruction set extension generation with considering physical constraints . In Proceedings of the 2nd International Conference on High Performance Embedded Architecture and Compilers . Lecture Notes in Computer Science , vol. 4367 , Springer-Verlag , Berlin Heidelberg , 291--305. I. W. Wu, S.-C. Huang, C.-P. Chung, and J.-J. Shann. 2007. Instruction set extension generation with considering physical constraints. In Proceedings of the 2nd International Conference on High Performance Embedded Architecture and Compilers. Lecture Notes in Computer Science, vol. 4367, Springer-Verlag, Berlin Heidelberg, 291--305."},{"volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). 273--278","author":"Yu P.","key":"e_1_2_1_27_1","unstructured":"P. Yu and T. Mitra . 2007. Disjoint pattern enumeration for custom instructions identification . In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). 273--278 . P. Yu and T. Mitra. 2007. Disjoint pattern enumeration for custom instructions identification. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). 273--278."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2560039","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2560039","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T08:10:21Z","timestamp":1750234221000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2560039"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3,10]]},"references-count":27,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2014,12,5]]}},"alternative-id":["10.1145\/2560039"],"URL":"https:\/\/doi.org\/10.1145\/2560039","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2014,3,10]]},"assertion":[{"value":"2012-09-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-03-10","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}